-Need of decap cells
-How Decap cells work
-Sources of ESD
-Latch up effect
Decap is short for decoupling capacitors.
Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail.
Need of decap cells
Added in the design between power and ground rails to counter functional failures due to dynamic IR drop.
Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch. Due to this simultaneous switching a high current is drawn from the power grid for a small duration.
Now consider, If the power source is far away from a flop the chances are that this flop may not be getting enough power for stable functioning due to IR Drop.
To overcome this decaps are added.
How they work
At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid.
It’s a capacitor that goes between VDD and GND in parallel with the rest of your logic gates. When your logic gates draw a high amount of current, this capacitor provides extra charge close to that circuit. When your logic gates aren’t drawing current, the capacitor charges up to maximum capicity and sits there waiting to be discharged.
One problem in usage of decaps is that these add to leakage current. Decaps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is.
Decap cells are generally placed near high activity clock buffers
Since they add to leakage, we need to make sure they are use effeciently in the design
ESD (ElectroStatic Discharge)
ESD is a transient discharge of static charge that arises from either human handling or a machine contact.
Electrostatic Discharge (ESD) is a charge balancing process between two objects at different potential
Although ESD is the result of a static potential in a charged object, the energy dissipated and damages made are mainly due to the current flowing through ICs during discharge.
The basic phenomenon of ESD is that is a large amount of heat is generated in a localized volume significantly faster than it can be removed, leading to a temperature in excess of the materials’ safe operating limits.
1.pn-junction may melt.
2.Gate oxide may have void formation.
3.Metal interconnects & Vias may melt or vaporization, leading to shorts or opens.
4.Gate-oxide breakdown is another form of ESD damage
Why ESD is Critical ?
The aggressive decrease in physical dimensions and increase in doping in modern CMOS technology result in a significant decrease in gate-oxide thickness and pn-junction width require less energy and lower voltages to destroy MOS devices.
The level of ESD stress, however, does not scale down with the technology.
Principle Sources of ESD in IC’s
Human Handling – A person walking on a synthetic floor can accumulated up to 20 kV. This voltage is discharged when the person touches an object that is sufficiently at ground. Charge exchange occurs between the person and the object in a very short time duration. Despite the fact that ESD events are of very short duration (0.2 – 200 ns), the massive current/voltage pulses can give fatal damage to integrated circuits.
Test and Handling Systems- Equipment can accumulate static charge due to improper grounding.
IC Itself is Charged During Transport / Contact With Charged Objects
ESD protection has typically been implemented by placing clamp circuits at appropriate locations on the chip that do 2 things.
1)First, provide a low impedance discharge path for the ESD.
2)clamp the signal voltage at a level that avoids dielectric breakdown.
These clamp circuits have been placed in the I/O and power/ground pads. Input pads are especially vulnerable since the input pin has to be connected to the gate of the input driver.
ESD events can also occur during packaging, assembly and test of the IC. And, in fact, charge buildup inside the chip can also cause ESD failures, especially from in-package capacitors and from on-chip memories.
To protect the IC from such high voltage pulses, ESD clamps are placed between every I/O pin and power supply pin.
ESD clamps turn on only when an ESD pulse is detected and turn off during normal operation.
ESD doesn’t just cause a potential problem when it happens, it can physically destroy the chip. Estimates are that as many as 35% of all in-field chip failures are due to ESD.
For example, if ESD is incorrectly handled and very high voltages end up on the gate of the chip, the discharge can destroy the thin oxide underneath the gate and make that transistor, and probably thus the whole chip, inoperable.
Since the thin oxide is getting thinner with each process node it is not surprising that ESD is a problem that is only going to continue to get worse.
These library cells connect the power and ground connections to the substrate and n-wells, respectively.
By placing well taps at regular intervals throughout the design, the n-well potential is held constant for proper electrical functioning.
They are traditionally used so that Vdd or GND are connected to substrate or n-well respectively. This is to help tie Vdd and GND which results in lesser drift and prevention from latchup.
The Antenna Effect
Plasma Induced Damage (PID) = Antenna Effect
Occurs during manufacturing process.
Antennae are floating conduction layers without shielding layer of oxide.
The random discharge of the floating node could permanently damage the transistor.
Since the gate dielectric is so thin, only a few molecules thick, a big worry is breakdown of this layer. This can happen if the net somehow acquires a voltage somewhat higher than the normal operating voltage of the chip.
Once the chip is fabricated, this cannot happen, since every net has at least some source/drain implant connected to it. The source/drain implant forms a diode, which breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse breakdown), and does so non-destructively. This protects the gate oxide.
Chips are usually processed from the bulk up.
Current processes have > 8 or 10 layers of interconnect.
Reactive Ion Etching (RIE) -standard method for etching thin films in VLSI manufacturing.
This is a dry etching process and hence results in accumulation of charge.
During the IC manufacturing process, the metal layer is exposed to conditions that lead to the build-up of an electrostatic charge. The amount of charge that builds up depends on a number of factors; the most important from an antenna standpoint is how much metal is exposed. As more metal is exposed, the maximum charge that accumulates on the net that the metal is part of also increases. The substrate remains at ground since it is connected to the fabrication device. As a result a voltage gradient develops across the gate oxide. When this gradient becomes large enough, it is relieved via an explosive discharge (i.e. “lightning”). The problem is more significant at smaller technologies because the damage resulting from the discharge is more likely to extend across the entire length of the gate.
Antenna repair is accomplished by inserting a reverse-bias diode on the violating net as close to the gates being protected as practical. During normal chip operation, the reverse bias prevents electrons from flowing from the net through the diode and into the chip’s substrate. During fabrication, however, the charge on the net can build to the point where the voltage drop across the diode exceeds its break-down voltage. This voltage is greater than the normal
operating voltage, but less than the voltage at which an electrostatic discharge at the gate can be expected. When this happens, the diode allows electrons to flow from the net to the substrate and thus limits how much charge can accumulate on the net. The process is non-destructive, and it’s possible that the net could discharge through the diode several times during the fabrication process.
The “Antenna ratio” of an interconnect is used to predict if the antenna effect will occur.
Antenna ratio is defined as the ratio between physical area of the conductors making up the antenna to the total gate oxide area to which the antenna is electrically connected.
A higher ratio defines higher probability for the antenna effect.
Break signal wires and route to upper metal layers by jumper insertion.
All metal being etched is not connected to a gate until the last metal layer is etched.
Embedded Protection Diode
Connect reverse biased diodes to the gate of transistor.
During normal circuit operation, the diode does not affect functionality.
A jumper insertion is the most effective way of reducing antenna effect.
A jumper is a forced layer change from one metal layer to another, and then back to the same layer. Jumper insertion breaks up a long wire so that the wire connected to the gate input is shorter and less capable of collecting charge.
One advantage of jumper insertion is that it is fully controlled by the routing tool, while disadvantage is that it can potentially contribute to routing congestion problems in the upper metal layers.
Change the order of the routing layers. If the gate(s) immediately connects to the highest metal layer, no antenna violation will normally occur.
Add vias near the gate(s), to connect the gate to the highest layer used. This adds more vias, but involves fewer changes to the rest of the net.
Diode insertion near a logic gate input pin on a net provides a discharge path to the substrate so that build up charges cannot damage the transistor gate.
However the diode insertion increases cell area and slows timing due to the increase of logic gate input load.
Antenna Diodes cells
Diode Insertion after placement and route Connected of diodes, only to those layers with antenna violations.
One diode can be used to protect all input ports that are connected to the same output ports.
Add diode(s) to the net. A diode can be formed away from a MOSFET source/drain, for example, with an n+ implant in a p-substrate or with a p+ implant in an n-well. If the diode is connected to metal near the gate(s), it can protect the gate oxide. This can be done only on nets with violations, or on every gate (in general by putting such diodes in every library cell).
The “every cell” solution can fix almost all antenna problems with no need for action by any other tools.
However, the extra capacitance of the diode makes the circuit slower and more power hungry.