What is UVM-Uvm (Uvinersal verification methodology) is a Class library that provides building blocks needed to develop fast ,well structured and reusable verification components . It is based on OVM library with some modifications made on top of the proven OVM code, not a quantum leap over OVM The value of UVM is that it offers a single cross industry solution to the challenges of design verification Conceptualized in year 2009, introduced to user community in 2010, it’s an open standard i.e. it’s in open source format from Accellera (targeted for IEEE) with user community group site.
Why UVM – To answer this question one needs to look into the history of creation of concept of verification and UVM
Around the turn of this millennium SOC developers found that functional verification alone consumed more than 50% of their time and effort
Since there are so many proven and promising technologies for enhanced verification that SOC developers get really confused with.
All these are technologies are developed by companies to enhance the verification of complex SOC and IPs.Some are open source some are not.
Since in the coming years due to the complex structure of the chips the verification is also going to be very complex.So the need of the hour was to get something which is a standard throughout the industry .
Some of the verification technologies are
object oriented programming
constrained random stimulus generation
coverage based verification
assertion based verification
To remove this confusion about picking the best possible technologies among the above a methodology called UVM was born.
UVM guides you on when, where, why and how the various technologies should be used/applied for maximum efficiency
History and development of UVM as an open source methodology:
In year 2000 Verisity Design introduced best known practices for verification called Verification Advisor (vAdvisor).This was targeted for e user community i.e. various verification design patterns included in HTML format that touched many aspects of verification like stimuli creation, self checking TB’s, coverage models.
In year 2002 Verisity introduced the first verification library called the e Reuse Methodology popularly known as eRM.
component requirements(environment, agents, monitors and so on)
sequences and virtual sequences
object mechanism and much more of what exists in OVM today
eRM was enhanced from module to system level reuse, system level verification components, software level verification components
In year 2003 Synopsys came out with Reuse Verification Methodology Library (RVM) for its Vera Verification Language
packaging guidelines but did not include architecture guidelines, sequences, object mechanism etc.
RVM main feature was its callback solution borrowed from software design patterns
RVM was finally converted into System Verilog (SV) Verification Methodology Manual (VMM), Synopsys proprietary library that supported evolution of System Verilog Standard
In year 2006 Advanced Verification Methodology (AVM) was introduced by Mentor
AVM mainly leveraged OSCI SystemC Transaction Level Modeling (TLM) standard
AVM was the first open source verification solution
Cadence developed SV version of eRM this resulted in Universal Reuse Methodology (URM) in 2007
URM with open source TLM became very popular and most successful verification methodology
This resulted in Cadence and Mentor joining hands in 2008 to release OVM why because URM provided facility for high level methodology infrastructure whereas AVM provided low level TLM methodology
OVM came into picture and proved to be very good solution as open source
user community site www.ovmworld.org created for user’s help.The open source of these methodology helped them to gain the popularity among the user as companies do not have to pay huge to use these technologies .Most of the big EDA vendors are involved in development phase of these technologies.All the simulators for front end verification supported UVM for the verification.
In year 2010 OVM 2.1.1 chosen as basis for UVM
UVM is really useful in verification of complex IP blocks,Sub Blocks(Multiple IP system) or System on Chip (SOC’s) Designs
UVM is designed to work with HDL’s like VHDL, Verilog and HVL’s like e, System Verilog, SystemC
Currently in the industry most of the new testbench development has been going on which is in the UVM methodology.Most of the engineers in the college has stated using these methodology .
Lots of tools are in the market which dedicated to support the generation of UVM RAL model.These has emerged as the widely used open sourse methodology and in near future since most of the industry is using it.This will dominate the front end verification domain.So it is important for a verification engineer or those who are willing to make a career in front end verification of VLSI domain.