Floorplan Interview Question and Answer
The input to a floorplanning tool is a hierarchical netlist that describes the interconnection of the blocks (RAM, ROM, ALU, cache controller, and so on); the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks; and the logic cell connectors (the terms terminals, pins , or ports mean the same thing as connectors ). The netlist is a logical description of the ASIC; the floorplan is a physical description of an ASIC. Floorplanning is thus a mapping between the logical description (the netlist) and the physical description (the floorplan).
Differentiate between chip level design and block level design?
Ans. Any chip or product are usually designed by dividing the whole circuit in many partitions if it is not small enough to handle hierarchy of implementation. Each of these partitions is designed separately. The partitions or subsystem are assembled together to create full chip when these subsystem are done. These subsystem are called “block”, and designing it is called block level design and the assembly of these block will form full chip is called chip level design. Parameters of both are:
– Chip design requires several packaging; block design ends in a macro.
– Chip design uses all metal layes available; block design may not use all metal layers.
– Chip design has I/O pads; block design has pins.
What are the guidelines followed for good floorplan?
Ans. Steps followed with the aim of generating an optimum floor plan:-
- Defining the core area using Specify Floor Plan Form
- Defining ports specified by top level engineer.
- Placing the macros inside the core area.
- Placing the Macros which are communicating with each other, together with help of Fly Lines,
- Color by Hierarchy and Data Flow Diagrams.
- Avoid the placement of Macros in front of ports.
- Arrange the Macros to get contiguous core area.
- Defining halos
- Defining Placement and Routing blockages.
What are the factors deciding the minimum space required between two macros?
Ans. Factors deciding the space between channel are:-
- No. of pins of block(Pin density)
- Power stripes
- Power switch cells
- End cap and well tap cells
- Routing Pitch
- of Metal layers
What are the steps to be taken care while doing floorplaning?
Ans. Steps to be taken care while doing floorplanning are:-
-Consider connections to fixed cells when placing macros.
-Orient macros to minimize distance between pins.
-Reserve enough room around macros.
-Reduce open fields as much as possible.
-Reserve space for power grid.
-Orientation- It decides the direction of the pins of macros.
What is expected utilization at floorplan?
Ans. During floorplan you should target approximately 60%-65% utilization because you need to account for optimization and CTS.
Differentiate between flat and hierarchical design?
How will you validate your floorplan?
Ans. This checks will validate the floorplan:-
-Utilization should be under controls after floorplanning is done
-Pin placement should be proper
-Check Macro Pin Spacing
-Hard Macro Overlap check
-Report pin placement ( Pin Spacing, Pin Off Track, Shorts, Missing Shape )
-Check Boundary and Tap Cells Placement
-IO timing, Macro to macro timing, Macro to standard cell timing with margin.
-IR drop analysis
What are inputs and outputs of floorplan stage?
Gate level Netlist
Design Exchange format
Placement of I/O pad
Standard cell placement areas
What are floorplan control parameters?
Ans. Floorplan Control parameters are:-
- Aspect ratio is defined as the ratio of height to width
AR = height / width
- Total Utilization = (Area of standard cells + macros + IO )/ Total area of die.
In general 70 to 80% of utilization is fixed because more number of inverters and buffers will be added during the process of CTS in order to maintain minimum skew.
- Row Orientation-These rows are individual rows and the row area is utilized by the standard cells .If the channel area is reduced, better the utilization can be achieved. But reducing the channel area leads to short between Vss and Vdd. To avoid this, every rows are flipped so that Vdd of two rows can be joined together and Vss of two rows can be connected together. The utilization depends only on the row area, not the channel area.
What is core utilization?
Ans. Utilization defines the area occupied by standard cell, macros and blockages. In general 70 to 80% of utilization is fixed because more number of inverters and buffers will be added during the process of CTS (Clock Tree Synthesis) in order to maintain minimum skew.
Chip Level utilization: It is the ratio of the area of standard cells, macros and the pad cells with respect to area of chip.
Floorplan Utilization: It is defined as the ratio of the area of standard cells, macros, and the pad cells to the area of the chip minus the area of the sub floorplan.
Standard Cell Row Utilization: It is defined as the ratio of the area of the standard Cells to the area of the chip minus the area of the macros and area of blockages.
Difference between pad limited and core limited design?
Ans. Pad Limited Design
- If pad area is more than core area
- Large number of I/O pads and less number of logic I/O pads
- Here pad area decide the size of the die
Core Limited design
If core area is more than pad area
Core area decides the die size
What is floorplanning?
Ans. Floor planning is the starting step in ASIC physical design.Floor plan determines the size of the design cell (or die), creates the boundary and core area, and creates wire tracks for placement of standard cells.It is also a process of positioning blocks or macros and I/O pads. Floor planning also determines the area of core and die, placement of Macros and IOs and to define area/regions for the standard cells placement, routing and other purposes. Floor Planning takes into account the macro’s used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Floor planning also decides the IO structure, aspect ratio of the design
What is need for sanity checks at floorplan stage?
Ans. Sanity checks are done to make sure whether the inputs given by synthesis team are correct or not. The below mentioned sanity checks are done:
- check_design checks for certain problems like floating input/output ports or undriven output ports, any net without loads or with multiple drivers, cells or designs without inputs or outputs, tristate buses with non-tristate drivers.
- check_library checks the consistency between logic and physical libraries. It checks whether each cell described in the netlist has its corresponding physical library and logic information defined in timing library.
- check_timing checks whether all the paths in a design are constrained and also consistency prevails between the constraints. Basically, it will check whether all ports has its input/output delays specified and checks whether clock definition exists for all clock pins of all flops.
What is major advantage of using flip chip over wire bond package?
Ans. Flip-chip assembly and wire bonding are the principal methods for interconnecting ICs.
- While each offers strong advantages in certain types of applications, packaging is continuing to evolve into a segmented marketplace, with several factors dictating the most appropriate means of interconnection.
- Many of the advantages depend on the specific application details. Often, both processes offer advantages.
- An example is cost. The total cost for a wire-bonded package in the <600 IO range is typically much less than for an equivalent flip-chip package.
- But for a high volume application, with chips designed and die size minimized to take advantage of flip-chip’s efficient use of silicon real estate, wafer cost reductions can significantly lower the total cost per flip-chip package below that of the comparable wire bonded package.
- Wire-bond is cheaper than flip-chip interconnections.
- However, wire bond interconnections cause a higher power supply noise level in the power distribution network due to higher parasitics.
- In flip-chip technology, the parasitics are reduced by spreading the die pads along the surface of the chip and therefore reducing the noise.
What are flylines?
Ans. Fly/flight lines are virtual connections between macros and also macros to I/O pads. This helps the designer to get an idea about the logical connections between macros and pads. Fly/flight lines act as guidelines to the designer to reduce the routing resources to be used. On the basis of connectivity it shows, flight lines are of three types.
- Macro to macro fly lines– This shows the total number of connections between two macros. This gives an idea to the designer about which two modules to be placed closer.
- Pin to pin fly lines– If two macros are selected for pin to pin fly lines, the virtual connections are shown and the much preciously connection to exact pin to pin will be shown. This guides the designer to choose an appropriate cell orientation for the macros and as a resultant will be efficient routing.
- Macro to I/O fly lines– Macro to I/O flight lines shows the exact connection between the macro pins and the I/O ports of pins. This helps the designer to identify the macros to be kept at the corners of the die or block.