FLOORPLAN INTERVIEW QUESTIONS
In today’s world, there is an ever-increasing demand for SOC speed, performance, and features. To cater to all those needs, the industry is moving toward lower technology nodes. The current market has become more and more demanding, in turn forcing complex architectures and reduced time to market. The complex integrations and smaller design cycle emphasize the importance of floorplanning, i.e., the first step in netlist-to-GDSII design flow. Floorplanning not only captures designer’s intent, but also presents the challenges and opportunities that affect the entire design flow, from design to implementation and chip assembly.
- Differentiate between chip level design and block level design?
- What are the guidelines followed for good floorplan ?
- What are the factors deciding the minimum space required between two macros?
- What are the steps to be taken care while doing floorplaning?
- What is expected utilization at floorplan?
- Differentiate between flat and hierarchical design?
- How will you validate your floorplan ?
- What are inputs and outputs of floorplan stage?
- What are floorplan control parameters?
- What is core utilization?
- Difference between pad limited and core limited design?
- What is floorplaning?
- What is need for sanity checks at floorplan stage?
- What is major advantage of using flip chip over wire bond package?
- What are flylines?