- The most important concern in semiconductor industry before release to foundry is timing performance of chip.
- In semiconductor devices, metal interconnect traces are being used to connect various portions of the circuitry to realize the digital design.
- Towards advancement of semiconductor industry, the process technology is shrinking and these interconnect traces have been known to affect the performance of a design. As these traces are combination of resistance and capacitance that any how adds to some delay which directly impact timing.
- Basically, the timing analysis refer to the analysis of the design for timing issues.
- Two different timing analysis method/approach: Static timing analysis and timing simulation(Dynamic timing analysis)
- Dynamic Timing analysis ascertain the full behavior of design for which it requires all set of input data values to validate the timing characteristics of all possible paths.
- Dynamic simulation checks both the functionality of the design as well as timing requirements. For example if we have 10 input data values then it will validate 2 to the power of 10 times for complete analysis.
- Static Timing analysis verifies each and every path for timing violations without checking the functionality of the design. This approach is faster than timing simulation because there is no need to generate any kind of test vectors. That’s why STA is preferred way of timing analysis.
|Static timing Analysis||Timing Simulation|
|Static – does not depend upon the data values being applied at the input pins.||Stimulus is applied on input signals, resulting behavior is observed and verified, then time is advanced with new input stimulus applied, and the new behavior is observed and verified and soon|
|Validate if the design can operate at the rated speed, any timing violations||Only verify the portions of the design that get exercised by stimulus|
|Exhaustive and complete method i.e. the entire design is analyzed once||Difficult to do exhaustive verification i.e. different test vectors to verify all timing conditions of a design|
|Faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations||Cannot handle the effects of cross-talk and on-chip variations|