- npn or pnp silicon structure
- Small current into very thin base layer controls large currents between emitter and collector
Metal Oxide Semiconductor Field Effect Transistors
- nMOS and pMOS MOSFETS
- Voltage applied to insulated gate controls current between source and drain
MOSFETs over BJTs
1.Are smaller in size so occupy lesser silicon area, hence more chip density can be achieved.
2.Supports easy fabrication process.
3.Consume less power, so better performance
Digital CMOS (Complementary Metal Oxide Semiconductor) integrated circuits (ICs) have been the driving ‘force behind Very Large Scale Integration (VLSI) for high performance computing and other scientific and engineering applications. Features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits are the major factor that marks the increasing use of CMOS.
Four terminal device: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
◦Gate and body are conductors (body is also called the substrate)
◦SiO2 (oxide) is a “good” insulator (separates the gate from the body
This four-terminal device consists of a p-type substrate, in which two n+ diffusion regions, the drain and the source, are formed.
The surface of the substrate region between the drain and the source is covered with a thin oxide layer, and the metal gate is deposited on top of this gate dielectric.
The distance between the drain and source diffusion regions is the channel length L, and the lateral extent of the channel (perpendicular to the length dimension) is the channel width W.
Both the charnel length and the channel width are important parameters which can be used to control some of the electrical properties of the MOSFET.
A MOS transistor which has no conducting channel region at zero gate bias is called an enhancement-type (or enhancement-mode) MOSFET. If a conducting channel already exists at zero gate bias, on the other hand, the device is called a depletion-type.
In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device with p-type substrate is called an n-channel MOSFET.
Various regions of operation of MOSFET
MOSFET has three regions of operation: the cut-off region, the triode region, and the saturation region.
The cut-off region and the triode region are used to operate as switch. The saturation region is used to operate as amplifier.
Three regions of operation of a MOSFET
Cut-off region: When VGS < Vt, no channel is induced and the MOSFET will be in cut-off region. No current flows.
Triode region: When VGS ≥ Vt, a channel will be induced and current starts flowing if VDS > 0. MOSFET will be in triode region as long as VDS < VGS – Vt.
Saturation region: When VGS ≥ Vt, and VDS ≥ VGS – Vt, the channel will be in saturation mode, where the current value saturates. There will be little or no effect on MOSFET when VDS is further increased.
(By convention, all terminal voltages of the device are defined with respect to the source potential. Thus, the gate-to-source voltage is denoted by VGS, the drain-to-source voltage is denoted by VDS, and the substrate-to-source voltage is denoted by VBS.)
The simple operation principle of this device is:
Control the current conduction between the source and the drain, using the electric field generated by the gate voltage as a control variable.
Since the current flow in the channel is also controlled by the drain-,to-source voltage and by the substrate voltage, the current can be considered a function of these external terminal voltages.
Depending on the polarity and the magnitude of VG, three different operating regions can be observed for the MOS system:
accumulation, depletion, and inversion.
If a negative voltage VG is applied to the gate electrode, the holes in the p-type substrate are attracted to the semiconductor-oxide interface. The majority carrier concentration near the surface becomes larger than the equilibrium hole concentration in the substrate; hence, this condition is called carrier accumulation on the surface.
Now consider the next case in which a small positive gate bias VG is applied to the gate electrode. Since the substrate bias is zero, the oxide electric field will be directed towards the substrate in this case.
The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions behind. Thus, a depletion region is created near the surface.
Further increase in the positive gate bias. As a result of the increasing surface potential, the downward bending of the energy bands will increase as well.
Within this thin layer, the electron density is larger than the majority hole density, since the positive gate potential attracts additional minority carriers (electrons) from the bulk substrate to the surface.
The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called surface inversion. It will be seen that the thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting current between two terminals of the MOS transistor.
Once the surface is inverted, any further increase in the gate voltage leads to an increase of mobile electron concentration on the surface, but not to an increase of the depletion depth. Thus, the depletion region depth achieved at the onset of surface inversion is also equal to the maximum depletion depth, which remains constant for higher gate voltages.