- What are different types of Power?
Switching or Dynamic power (Major power consumption happens due to this component). It happens because of the continuous toggling of the devices. The frequent charging and discharging of capacitor is the reason of switching power dissipation.
Leakage Power:-The power that the device or any instance consumes when in the inactive state is called the leakage power. The silicon devices not being ideal switches have some leakage power.
Internal Power:-Power consumed due to internal capacitance is known as the internal power. Short circuit power is also internal power.
- What is the formula for Switching Power?
The Switching power is nothing but the Dynamic power consumed due to toggling of signals.
It is directly proportional to the operating frequency of the circuit, voltage applied, and the output load capacitance.
Where A is the Toggling factor
C is the output load capacitance
V is the voltage applied
F is the Frequency
- What is switching activity?
Switching activity is the measurement of changes of signal values either form 0 to 1 or from 1 to 0.
It is directly proportional to the switching power. So if switching activity increases, switching power consumption also increases.
- What is the impact of width variation of a wire on resistance?
Down the Technology node, the width decreases and resistance increases. On increasing the width the area for the current to flow increases and hence the same amount of current can now flow through a wider area. This tells us that the resistance decreases with increase in width of wire.
Resistance = (Resistivity x Length)/ Area
Area = Width x Thickness
So, Resistance inversely proportional to width, increase in width will decrease resistance and decrease in width increase resistance.
- What are the different types of IR drop analysis?
Static and dynamic are the 2 types of IR drop Analysis.
Static IR drop analysis can be done in the initial design phase itself because we do not need any toggling values of signal nets. We do not require transient time information of the design since in static analysis we perform IR drop analysis keeping all the nets at constant values. It highlights the EM problems in the design.
Dynamic IR drop Analysis is done after we have toggling information in the form of VCD file. It is a vector based IR analysis in which we check for the timing window where the power requirements are the highest. We perform Analysis on varying or toggling signal nets. RLC values of the network are considered for analysis.
- Difference between Vector and Vectorless analysis?
There are 3 types of analysis
Vectorless analysis (no toggling information is there)
Vector Based analysis (we have toggling or vector information from VCD file)
Mixed analysis (we use both the VCD file and user defined toggle values for the analysis) the cells that do not have toggling rates defined uses user defined values here.
Vectorless analysis is done when no VCD file is available. Then the estimate of toggling rate and switching times is made using values from the group of GSR file keywords.
In vector based analysis the toggling information is obtained from the VCD file defined by the keyword VCD_FILE in the GSR file.
- Which file contains function of a standard cell?
.lib file or Liberty File contains the functions of the standard cells. Other than that it also has timing and power related information of each standard cell.
- I want to take design information from one EDA tool to another which file i am going to dump for this?
DEF file “Design Exchange Format”
Contains all the design related information like the locations of the pads, cells, information on power rings, power strips, site values, location of macros etc.
- Which file contains physical information of all the cells, macros, Pads?
PLOC, LEF file (cell lef)
The PLOC file contains the pad location of power and ground pads. It gives us the Voltage sources location on the chip.
The Cell lef has the Macros and standard cells physical information like the length, width of cell. Signal and PG pins of cells, site of the cell, cell description, capacitances, etc.
- Which files we use for getting RC values of signal nets and Power nets during RH analysis?
Standard Parasitic Extraction Format
- What are 4 Fundamentals for Physical Design?
Floor planning (designing the blue print of the chip and then power planning)
Placement (placing the standard cells and macros)
CTS (Routing clock and Meeting clock requirements for each cell)
Routing (signal detail routing)
- Which file we use for getting Power ground Pad location?
- Which file contains all the technology related information, as per RH flow?
It contains many other information related to the metal and via like the thickness, width, spacing, EM values, resistance values at given temperature, dielectric constant, dielectric thickness etc.
- What is the impact of temperature on resistance?
The Resistance of different Material varies differently with change in temperature mainly due to a change in the dimensions of the component as it expands or contracts.
Materials which are classed as CONDUCTORS tend to INCREASE their resistivity with an increase in temperature. INSULATORS however are liable to DECREASE their resistivity with an increase in temperature.
The current flowing in the material is due to the movement of “free electrons” and the number of free electrons within any material compared with those tightly bound to their atoms is what governs whether a material is a good conductor (many free electrons) or a good insulator (hardly any free electrons).
The effect of heat on the atomic structure of a material is to make the atoms vibrate, and the higher the temperature the more violently the atoms vibrate.
In Semiconductor Material
With increase in temperature, the conductivity of the semi-conductor material increases. As with increase in temperature, outermost electrons acquire energy and hence by acquiring energy, the outermost electrons leave the shell of the atom.
Hence with increase in temperature, number of carriers in the semiconductor material increases and which leads to increase in conductivity of the material. So we call the semi-conductor material have negative temperature coefficient i.e. with increase in temperature, resistance decreases.
- In what form package is contributing to IR drop, give formula only for total drop?
Power inductance is also causing some Voltage drop problems on package. The inductance can be because of power bump or power pin.
>>> Ldi/dt (voltage drop due to inductance)
Total Voltage Drop= IR + Ldi/dt
- What is the flow for Power and IR drop analysis?
->> Data Preparation (GRS file, STA file, gds2def file, .tech file, Spef file)
->> Importing the design
->> Setup design (loading the design data)
->> Power calculation (Computing power for instances and signal nets)
->> Extraction of PG values ( PG weakness Analysis)
->> Defining Package parasitic (Pad, wirebond and package RLC values defined here)
->> performing static analysis (IR drop Analysis)/ DvD Analysis
->> Checking IR issues with Reports and different Maps (power density map, chip layout map,
leakage power map, instance power map, instance freq. map etc.)
->> Saving the session details
->> Exploring Reports with Explorer utility of RH
- What are the causes for Static and Dynamic issues?
The major Causes or reasons for Static IR Issues are:-
Physically unconnected instances
Instances with floating power or ground pins
Bad quality of Pad placement
Lesser number of power strips or non-uniform power strips
High Resistance of instances in design
The Causes for Dynamic issues are:-
The instances have different power dissipation on different states.
The toggling of Signal nets has huge power dissipation at different timing instant.
High driving cells in the design
High Threshold cells used
- Mention solution for Static and Dynamic IR drop issues?
Solution to Static IR drop Problems
- Using more number of power stripes
- Multi-cut VIA’s can be used. Having more paths for the current to flow from one metal to another, so lesser IR drop.
- Increasing the width of power nets will reduce the resistance and hence IR drop. But it can only be increased up to a limit.
- Spreading logic in the area properly
- Proper allocation of power and ground pads.
Solution for Dynamic voltage drop problems:-
Decap Cells Insertion
A decap cell is inserted in parallel to the instance for reducing the IR drop. The capacitor is nothing but power storage.
We consider the toggling percent in the chip and not the density of cells while doing
Eg a region of chip has 50% toggling but 60% cell density, while the rest part has just 20% toggling and 70% density then we need to uniform the high toggling region by spreading it.
High driving cells have High IR drop so cell downsizing will help reduce IR drop in the circuit.
HVT to LVT conversion
The HVT cells will have High IR drop due to high threshold value so changing the HVT to LVT will help in solving Dvd issues.
Skewing the clock without disturbing the timing on critical paths
More Number of flops switching simultaneously, so more IR drop and more power dissipation, so we some slew or delay.
- What is the issue we will see if a wire’s current requirement is very high than its capacity?
EM effect will take place after certain interval of time. The Electromigration effect happens due to the long term of current flowing in a wire and causing the Ions to move from their respective location leading to a short or open in the wire.
- What factor causes ESD issues?
ESD is short for Electrostatic Discharge. It is the flow of charge between 2 bodies which are at different potential. In VLSI this leads to charge accumulation on the metal layers and leads to short circuit of the gate terminal of the transistor device.
The main factors that make ESD more likely to occur are:-
- moving people
- improper grounding
- unshielded cables
- poor connections
- moving machines
21 What is the use of switch cells, how those are placed in the design?
Switch cells are nothing but transistors connected in a way to switch a circuit ON and OFF. By using high-Vt transistors as header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly reduced.
MTCMOS switches can be implemented in various different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into every standard cell, or they can be used to switch off a large design block of standard cells.