Roles :- Technical Lead 6+ and Sr. Engineer 4+
Functional Verification Engineer for DDR PHY Controller IP
The work involved will be creating verification environment for new IP, working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage.
The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team particularly with respect to functional and code coverage.
BE/ BTech / ME/ MTech – Electrical / Electronics / VLSI with 4 -6 yrs of experience as a design and verification engineer, with a large portion of the recent work experience on verification environment development.
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development are a must.
System Verilog experience and experience with UVM based functional verification environment development is required.
Latest DDR Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is a must.
AXI3/4 and/or AHB experience is a desirable.
Salary: Best in the Industry, No Variable Pay
Industry: Semiconductors / Electronics
Functional Area: Engineering Design, R&D
Role Category: Technical Lead/Project Lead
Role: Technical Lead/Project Lead
System Verilog, UVM, Design Verification, VLSI, Test Planning, DDR PHY Controller IP, Functional Verification, DDR Protocol, AXI, AHB.