In this role you will responsible for architecture, development and correlation of power estimation models/tools for NVIDIAs GPU and Tegra SOC chips. Help architect and develop power estimation models for use-case, leakage, and IO power. Contribute to designing the tools based on these models and their testing methodology/infrastructures. Correlate/calibrate these models using measured silicon data. Help study/contribute to Performance/Watt improvement ideas for GPUs and Tegra SOCs.
– MSEE/MSCE/PhD, with specialization/experience related to Power/Performance estimation techniques.
– 3+ years of experience. Strong background in power estimation techniques, flows and algorithms.
– Understands power basics including transistor-level leakage/dynamic characteristics of VLSI circuits.
– Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS) etc. is desirable.
– Good software programming skills. Python/Perl/C++ preferred. Good skills with object oriented programming and design.
– Good Understanding of mathematical optimization techniques is a highly desirable.
– Good understanding of performance simulators, analysis and monitoring used in modern processor architectures (GPU is a plus).
– Exposure to lab setup including power measurements equipment such as scope/DAQ is with ability to analyze board level power issues is a plus-
– Exposure to power analysis EDA tools such as PTPX/EPS is a plus
Salary: Not Disclosed by Recruiter
Industry:IT-Hardware & Networking
Functional Area:Engineering Design , R&D
Role Category:Engineering Design
Role:Senior Design Engineer