------------------- TLM : transaction Level ModelingPUSH:port:uvm_blocking_put_port(producer) imp:uvm_blocking_put_imp(consumer)method: … [Read more...]
UVM Typical TestBench Structure
UVM:TYPICAL TESTBENCH STRUCTURE Top most module - uvm_root(uvm_top) - test case(component) - env - sub_env, scoreboard, checker - agents(master, slave) - … [Read more...]
Understanding if else and case statements in verilog
Ifelse Case1. Inifelse , it checks all the condition before it gets … [Read more...]
Interview Questions in verilog & Digital
Digital Interview Questions::Ques-> Draw hardware for 2 bit comparator. Ques-> Draw clock multiplier. Ques-> Hardware for clock divider by … [Read more...]
VLSI and hardware engineering interview questions
Explain why & how a MOSFET works Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor … [Read more...]
Special Cells used in VLSI Physical Design
Decap cells -Need of decap cells -How Decap cells workESD cells -ESD effect -Sources of ESD -ESD ProtectionTap cells -Latch up … [Read more...]
