Gate Level Simulation labs.
Hands-on GLS labs — simulate a gate-level netlist, back-annotate SDF, and debug the X, reset, and timing failures on a real waveform. These labs land as the curriculum rolls out. The tutorials are live now — start there.
Coming soon· Tutorials planned
What this subject will cover
- Simulate a synthesized netlist against its RTL.
- Back-annotate real delays with SDF.
- Root-cause an X-propagation failure.
- Debug a setup/hold timing violation.
- Sign off a clean full-timing GLS run.