Design for Testability labs.
Hands-on DFT labs — make real logic scannable, run ATPG, and debug a scan-chain failure the way silicon bring-up does. These labs land as the curriculum rolls out. The tutorials are live now — start there.
Coming soon· Tutorials planned
What this subject will cover
- Make a flip-flop and counter scannable.
- Insert scan chains and pass design-rule checking.
- Run ATPG and read the coverage report.
- Debug a scan-chain and a pattern-mismatch failure.
- Sign off scan + compression + ATPG on a small IP.