Combinational Loops and Why to Avoid Them

1. Engineering intuition — a circuit chasing its own tail

Combinational logic is supposed to settle: present the inputs, the gates resolve, the outputs hold a value. A combinational loop can never settle, because an output is wired back to feed its own input with no memory in between. Each new value forces another new value, which forces another — the circuit chases its own tail forever. There is no "answer," because the question depends on the answer. That is why combinational feedback is forbidden: it is not a function of the inputs at all.

2. Formal explanation — feedback with no register

-- DIRECT loop: y depends on itself through pure logic.
y <= y xor a;                 -- each delta flips y → schedules another flip → never settles
 
-- INDIRECT loop: a cycle through several combinational signals.
p <= q and a;
q <= p or b;                  -- p depends on q depends on p → a combinational cycle
 
-- Inside a combinational process, the same thing: an output read into its own expression.
process (all) begin
  z <= z nand c;              -- z is a function of itself → loop
end process;

A combinational loop is any path from a signal back to itself through only combinational logic — no flip-flop, no clocked register. With no memory to hold a value across the cycle, the logic has no fixed point (or an unstable one), so it cannot represent a function of the inputs.

3. Simulation interpretation — oscillation and the iteration limit

By the delta-cycle model (lesson 3.4), a combinational loop schedules a new value every delta at the same simulation time, so the engine spins delta cycles indefinitely and either oscillates or aborts with a delta-cycle / iteration-limit error — its way of reporting "this logic has no stable solution." Real time never advances because the design never settles.

4. Hardware interpretation — why it is unusable

5. Debugging example — the delta-iteration-limit hang

Expected: combinational logic settles. Observed: the simulator hangs or aborts with an iteration-limit / delta-cycle error, and the offending signal shows endless toggling or X at one time point. Root cause: a signal depends combinationally on itself — a direct self-reference or a cycle through several signals — with no register, so there is no fixed point. Fix: break the loop with a register (clocked feedback), or remove the unintended feedback (often an accidental self-read or a miswired cross-coupling). Engineering takeaway: an unbounded burst of delta cycles at one time is the simulator telling you the combinational graph has a cycle — find the self-dependence and put a register (or remove it).

-- BUG: combinational self-feedback → no fixed point → iteration-limit.
-- y <= y xor a;
-- FIX: register the feedback → a toggle flip-flop, one defined value per clock.
process (clk) begin
  if rising_edge(clk) then
    y <= y xor a;            -- now y depends on its PREVIOUS clocked value → stable
  end if;
end process;

6. Common mistakes & what to watch for

• Accidental self-read in a combinational process. Reading an output into its own expression makes a loop; compute into a variable or break with a register.
• Cross-coupled combinational signals. Two signals each driven from the other (with no register) form a cycle; this is how latches/oscillators sneak in.
• Ignoring iteration-limit warnings. They almost always mean a real combinational loop; treat them as errors.
• Trying to build a latch/oscillator on purpose in RTL. Modern synchronous design avoids both; if you truly need feedback, register it.
• Confusing a loop with a long combinational path. A loop has no fixed point; a long path settles (just slowly) — different problems with different fixes.

7. Engineering insight & continuity

A combinational loop is the precise opposite of what combinational logic is for: instead of a function that settles, it is a self-reference that cannot. The rule is absolute in synchronous design — never create combinational feedback — and the cure is always the same: insert a register so the feedback depends on the previous clocked value, not the instantaneous one. That single fix is profound, because it is sequential logic: a circuit whose output depends on stored state updated on a clock edge. Module 6 closes here, and Module 7 — Sequential Logic Design — begins exactly where this fix leads: the clocked process, flip-flops, registers, counters, and shift registers, where controlled feedback through state is not a bug but the entire point.

8. Summary

A combinational loop is a signal that depends on itself through pure logic with no register, so it has no stable value: simulation oscillates or hits the delta-iteration limit, and hardware becomes an uncontrolled oscillator or race. It violates the no-feedback rule of combinational design. The fix is to break the path with a register — which turns the illegal loop into deterministic sequential logic, the subject of the next module.