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VHDL · Chapter 3.9 · Signals & Hardware Behavior

Signals as the Model of Real Wires

This is the lesson that ties the module together. Every topic so far has been a facet of one idea: a signal is a wire. Declaration gives the net a home in the hierarchy, a driver is the source that puts a value on it, and delta cycles are how the value updates. Resolution settles what happens when two drivers share the net, inertial and transport delays model how a value propagates along it, and initial values model what it carries before anything drives it. Hold all of that as a single picture, a net with a source and update rules, and you can read any RTL by asking two questions: what drives this wire, and when. This capstone also maps the model onto synthesis, showing how a combinational signal becomes a wire and a clocked signal becomes a register's output.

Foundation14 min readVHDLSignalsWiresSynthesisMental ModelRTL

1. Engineering intuition — one model, many facets

A schematic net is dead simple: it is a wire with exactly one source (or, on a bus, a resolved set of sources) and some fanout that reads it. Everything you learned in this module is just that picture made precise for simulation. When you stop thinking of a signal as a software variable and start seeing it as a net with a driver, the whole language clicks: assignments are drivers projecting values, delta cycles are how the net settles, and metalogical values are the net's honest report of contention or power-on uncertainty.

2. Formal explanation — the facets, assembled

A signal is the simulation model of a net, and each earlier lesson defined one facet of it:

one_signal_every_facet.vhd
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
signal data : std_logic_vector(7 downto 0) := (others => 'U');
-- 3.3 declaration/scope : 'data' is a net living in this architecture, visible to its readers
-- 3.5 driver            : whichever process/concurrent statement assigns 'data' is its source
-- 3.4 delta cycle       : an assignment updates 'data' one delta later, then wakes its fanout
-- 3.6 resolution        : if two sources drive 'data', a resolution function combines them ('X' on conflict)
-- 3.7 inertial/transport: a delayed assignment's pulse-handling models the wire's propagation
-- 3.8 init / 'U'        : 'data' carries its initial value (here 'U') until a driver acts

There is no separate machinery for each bullet — they are all aspects of "a net, sourced by a driver, updated by the engine."

3. Production-quality RTL — combinational net vs registered net

The single most useful distinction the model gives you is combinational wire versus registered net, decided entirely by where the driver lives:

wire_vs_register.vhd
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
 
-- Combinational signal: a WIRE driven by logic, recomputed whenever inputs change.
sum <= std_logic_vector(unsigned(a) + unsigned(b));    -- a net = an adder's output wire
 
-- Registered signal: the net is a FLIP-FLOP output, updated only on the clock edge.
process (clk)
begin
  if rising_edge(clk) then
    acc <= acc + unsigned(a);     -- 'acc' is a register's output net
  end if;
end process;

What hardware does this become? sum is the output wire of a combinational adder; acc is the output net of an 8-bit register fed by an adder. Same signal abstraction, two structures — distinguished only by whether the driving statement is combinational or clocked.

4. Hardware interpretation — signals map straight to nets

signal facets mapping to hardware: net, driver, resolved bus, register vs wireconcurrent /comb processclocked process≥2 sourcessignalthe simulation model of anetcombinational driver→ a WIRE (gate output)clocked driver→ a REGISTER output netmultiple drivers→ a resolved/tristate BUS12
The unified signal model and its hardware mapping. A signal is a net; its facets correspond to real structure: declaration/scope sets where the net lives in the hierarchy; the driver is the gate/register output that sources it; multiple drivers map to a resolved bus; the delta/update mechanism is just zero-delay settling of that net; init/'U' is its power-on state. A combinational driver makes the net a wire; a clocked driver makes it a register output. Reading RTL is reading this map backwards: from each signal to the source that drives it.

5. Simulation interpretation — the net's life in one timeline

The event-driven engine (lesson 3.4) plays out the same story for every net: it exists from elaboration with an initial value, takes new values from its driver via delta updates, and wakes its fanout each time it changes.

simulation timeline summarising a net's life from elaboration through delta updatesElaborationnet created (3.3)Initial value':=' or 'U' (3.8)Event wakes driverinput/clock change (3.5)Driver schedulesvaluetransaction onto projectedwaveform (3.5/3.7)Delta cycle updatenet takes value, resolvedif needed (3.4/3.6)Fanout wakesreaders re-evaluate; looprepeats12
The life of a net, as the simulator runs it — the recurring Module-3 timeline. The net is created at elaboration and holds its initial value; an event wakes the driving process, whose variables update immediately and whose signal assignment schedules a new value; the process suspends; one delta later the net takes the driver's value (resolved if multiply driven); the fanout wakes and the cycle repeats. Every lesson in this module is one labelled step of this loop.

A net's life: starts 'U', a driver defines it, then it tracks its source

8 cycles
A net's life: starts 'U', a driver defines it, then it tracks its sourcet=0: nets hold their initial value ('U')t=0: nets hold their i…'a' is driven → a defined wire value'a' is driven → a defi…registered 'acc' takes its driver's value on the clock edgeregistered 'acc' takes…clkaU3355229accUU33881010t0t1t2t3t4t5t6t7
The combinational net 'a' becomes defined as soon as its driver acts; the registered net 'acc' updates only on clock edges, one driver-transaction per edge. Both are the same signal abstraction — a net sourced by a driver — differing only in whether that driver is combinational or clocked. Reading the waveform is reading the drivers.

6. Debugging example — debugging by thinking in wires

Expected: a net carries the right value. Observed: it is wrong, stale, or 'X'. Method: treat the signal as a wire and ask the two questions. What drives it? — find the single driving statement (or, if several, you have an unintended multi-driver, lesson 3.6). When does that driver update? — combinational (any input change) or clocked (only on the edge); a stale value usually means the driver did not run (sensitivity list, lesson 3.5) or you expected combinational behaviour from a registered net. Fix follows from the answer. Engineering takeaway: nearly every signal bug resolves to "wrong driver" or "driver updated at the wrong time" — the wire model turns vague symptoms into those two precise questions.

wire-thinking in action
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
-- Symptom: 'flag' never changes. Wire questions:
--   What drives it? -> this process is its only driver. Good, single source.
--   When does it update? -> process(en) — only wakes on 'en', not on 'cond'.
-- Root cause: 'cond' changes are ignored; driver never re-runs for them.
process (en) begin            -- WRONG sensitivity
  flag <= en and cond;
end process;
process (en, cond) begin      -- FIX: driver re-runs on every input
  flag <= en and cond;
end process;

7. Common mistakes & what to watch for

  • Thinking of signals as software variables. They are nets with drivers; their update is scheduled, not immediate, and their value is whatever a driver projects.
  • Ignoring "what drives this." Every net needs a source; an undriven net sits at 'U', and a doubly-driven net resolves (often to 'X').
  • Confusing combinational and registered nets. The driver's context (clocked or not) decides; expecting a registered net to react combinationally is a classic error.
  • Forgetting the engine is event-driven. A net changes only when its driver runs and schedules a new value — not "continuously" in the software sense.
  • Treating 'X'/'U' as noise. They are the net's honest report of conflict or uninitialised state; trace them, do not mask them.

8. Engineering insight

The signal-as-wire model is the single most valuable abstraction in RTL design because it makes reading and writing hardware the same activity. Writing RTL is declaring nets and the drivers that source them; synthesis is making those nets and sources physical (wires, gates, registers, buses); debugging is asking what drives a net and when. Once this model is automatic, the rest of VHDL — processes, combinational and sequential logic, FSMs — is just ways to build drivers for nets you have already learned to reason about.

9. Summary

A signal is the simulation model of a real wire: declaration gives it a home, a driver sources it, delta cycles update it, resolution settles multiple drivers, delay models propagation, and 'U'/initial values model its power-on state. In synthesis a combinational driver makes the net a wire and a clocked driver makes it a register output. Read any RTL by asking what drives each net and when it updates.

10. Learning continuity

You can now reason about a single net and its driver completely. Real designs are many nets and drivers, all alive at once — which is the defining property of hardware and the subject of the next module. The Concurrent Execution Model shows how every statement in an architecture runs in parallel, event-driven, exactly like the always-active gates these wires connect — turning the single-wire model you just mastered into a full, concurrently-evaluated design.