Synchronous Reset

1. Engineering intuition — reset is just another input, sampled on the edge

A synchronous reset does not get any special treatment from the flip-flop — it rides in on the data side and is sampled at the clock edge like the data itself. When asserted, at the next edge the register loads its reset value instead of its normal next value; between edges, the reset (asserted or not) does nothing. This makes the reset behave exactly like the rest of your synchronous logic: predictable, edge-aligned, and easy for tools to reason about. The trade is that, with no clock, a synchronous reset cannot do anything — it needs an edge to take effect.

2. Formal explanation — the reset test inside the edge guard

library ieee; use ieee.std_logic_1164.all;
-- SYNCHRONOUS reset: the reset is tested INSIDE rising_edge → sampled at the edge.
sync_rst : process (clk)                 -- ONLY clk in the sensitivity list
begin
  if rising_edge(clk) then
    if rst = '1' then q <= '0';          -- reset value, applied AT the edge
    else              q <= d;
    end if;
  end if;
end process;

The defining feature: the if rst = '1' test is inside if rising_edge(clk), and the sensitivity list contains only clk. So the reset is evaluated when the clock ticks — it is a synchronous input. The reset value ('0' here, or IDLE for an FSM) is loaded on the edge where rst is sampled high.

3. Production RTL — synchronous reset across a block

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
ctrl : process (clk)
begin
  if rising_edge(clk) then
    if rst = '1' then                    -- one synchronous reset for the whole block
      state <= IDLE; count <= (others => '0'); valid <= '0';
    else
      state <= next_state;
      if en = '1' then count <= count + 1; end if;
      valid <= in_valid;
    end if;
  end if;
end process;

What hardware does this become? Each reset register gets a multiplexer on its D input that selects the reset value when rst is high, all sampled by the normal clock. There is no separate reset path to the flip-flop's clock or asynchronous pin — the reset is folded into the data logic. To synthesis and timing tools this is ordinary synchronous logic, which is exactly why it is easy to constrain.

4. Hardware interpretation — reset folded into the D logic

5. Simulation interpretation — effect on the next edge

6. Debugging example — the reset that was too narrow, or no clock

Expected: the design resets. Observed: it intermittently fails to reset, or never resets at all. Root cause: for the intermittent case, the synchronous reset pulse was narrower than a clock period (or fell between edges), so no edge sampled it; for the never-resets case, the clock was not running when reset was applied (synchronous reset needs an edge). Fix: hold the synchronous reset for at least one full clock (several, to be safe) and ensure the clock is running during reset; if reset must work without a clock, an asynchronous reset is required instead. Engineering takeaway: a synchronous reset is sampled at the edge — it must be wide enough to be caught and needs a live clock; otherwise it silently does nothing.

-- A synchronous reset must be held >= 1 clock (typically several) and needs a running clock.
-- Pulse rst high for multiple cycles at startup so every flip-flop samples it.
if rising_edge(clk) then
  if rst = '1' then q <= '0'; else q <= d; end if;
end if;

7. Common mistakes & what to watch for

• Reset pulse narrower than a clock. It can fall between edges and be missed; hold it for several clocks.
• Expecting reset with no clock. Synchronous reset needs a running clock; without one, nothing happens.
• Putting rst in the sensitivity list. Only clk belongs there; a synchronous reset is sampled at the edge, not reacted to immediately.
• Forgetting reset adds data-path logic. The reset mux is on the critical path of the D input; in timing-tight designs it costs a little.
• Assuming sync reset is always best. It needs a clock and cannot reset a stopped design; some flows (and FPGA flip-flops with dedicated async pins) prefer asynchronous reset — the next lessons compare.

8. Engineering insight & continuity

A synchronous reset keeps everything in one clean timing domain: the reset is ordinary synchronous logic, a mux on the data input sampled at the edge, so timing analysis, glitch filtering, clock gating, and scan all just work. The price is a running clock and a reset wide enough to be sampled, plus a little data-path logic. That trade-off — clean timing versus needing a clock — is exactly what you weigh against the alternative. The next lesson covers the other style, Asynchronous Reset, which takes effect immediately without a clock by using the flip-flop's dedicated reset pin, before Synchronous vs Asynchronous Reset puts the two side by side.