What VHDL Is and Why It Exists

1. Intuition — a schematic written in text

Open any VHDL file and your instinct, shaped by C, Python, or Java, is to read it top to bottom: line 1, then line 2, then line 3. Stop. VHDL is not describing a sequence of steps a processor will perform. It is describing a circuit — wires, gates, and flip-flops that all exist at once and all react in parallel.

Think of a VHDL file the way you think of a schematic. On a schematic, an AND gate and an OR gate on opposite corners of the page are both "running" all the time; neither waits its turn. VHDL is that schematic, expressed as text instead of symbols. The order you write things in mostly does not matter — what matters is what is connected to what.

2. Why hardware needs its own language

A normal programming language assumes one thing happens at a time on a processor. Hardware is the opposite: a chip is millions of gates switching simultaneously. You cannot capture "all of these things happen at the same time, and this output depends on those three inputs the instant any of them changes" in a language built around sequential statements.

That is why HDLs (Hardware Description Languages) exist. VHDL — VHSIC Hardware Description Language — was created so engineers could:

• describe a circuit's structure and behaviour precisely,
• simulate it to check it behaves correctly before committing to silicon, and
• synthesize it — have a tool turn the description into an actual gate-level netlist for an FPGA or ASIC.

VHDL and Verilog are the two dominant HDLs. VHDL is strongly typed and verbose by design — it favours catching mistakes at compile time, which is why it is common in FPGA, aerospace, and defence work.

3. What VHDL can describe

A serious HDL has to express every kind of digital hardware. VHDL describes:

• Combinational logic — outputs that depend only on current inputs (gates, muxes, adders, decoders).
• Sequential logic — outputs that depend on a clock and stored state (flip-flops, registers, counters, state machines).
• Interfaces — the named input/output boundary of a block (its entity).
• Hierarchy — large designs built by connecting smaller blocks together.

A minimal but complete VHDL design always has the same three parts — a library section that pulls in standard types, an entity that declares the interface, and an architecture that describes the logic:

library ieee;                       -- choose the resources we need
use ieee.std_logic_1164.all;        -- brings in std_logic / std_logic_vector
 
entity and_gate is                  -- the interface (the "black box")
  port (
    a : in  std_logic;
    b : in  std_logic;
    y : out std_logic
  );
end entity and_gate;
 
architecture rtl of and_gate is     -- the implementation (what's inside)
begin
  y <= a and b;                     -- ONE concurrent statement = ONE AND gate
end architecture rtl;

You will meet entity and architecture properly in 1.5 — here, just notice the shape: declare an interface, then describe the logic behind it. The single line y <= a and b; is not "assign a value to y"; it is "wire y to the output of an AND gate driven by a and b," permanently.

4. Where VHDL fits — one source, two tools

The most important thing to understand about your VHDL source is that two different tools read it for two different reasons, and they do not interpret it identically:

• Simulation answers "does it behave correctly?" The simulator pretends to be the hardware over time and shows you waveforms. Nothing is built.
• Synthesis answers "what gates does this become?" The synthesizer keeps only the synthesizable subset of VHDL and produces a netlist for real silicon.

Some VHDL is for simulation only (file I/O, time delays, testbench stimulus); the rest must be synthesizable. Knowing which is which is a skill the later lessons drill.

5. Hardware over time — reading a tiny example

Simulation observes hardware behaviour across time. For our AND gate, the output y is simply a and b at every instant — when both inputs are high, the output is high; otherwise it is low. There is no clock and no memory, so y tracks its inputs continuously:

Notice there are no clock edges driving y. That is the signature of combinational logic, and it is exactly what y <= a and b; describes.

6. Common mistakes & what to watch for

• Reading VHDL as software. The number-one beginner error. Statements in an architecture are not executed in order — they describe gates that all run at once.
• Expecting "line order" to set behaviour. Swapping two concurrent assignments changes nothing; what matters is the connectivity, not the text order.
• Assuming everything you write becomes hardware. Delays (after 10 ns), file I/O, and wait for time are simulation-only — a synthesizer ignores or rejects them.
• Forgetting the library / use lines. Without use ieee.std_logic_1164.all; the std_logic type is unknown and the file will not compile.

7. Summary & next step

VHDL is a hardware description language: you describe a parallel circuit, then simulate it for correctness and synthesize it into gates. A minimal design is always library → entity → architecture, and the same source is read two ways — as a behavioural model and as a recipe for real hardware.

You have seen entity and architecture in passing. Before we open them up, the next lesson steps back one level to the design units — the compilable building blocks (entity, architecture, package, package body, configuration) that VHDL files are actually made of, and how they live in a library.