AXI vs AHB vs APB — Complete AMBA Bus Comparison for RTL & SoC Designers

The three-letter acronyms AXI, AHB, and APB appear on nearly every System-on-Chip block diagram ever drawn, in nearly every RTL job description, and in nearly every digital-design interview. They are the load-bearing walls of the AMBA (Advanced Microcontroller Bus Architecture) family — the on-chip interconnect standard from Arm that quietly moves every byte inside your phone, your laptop, your car, and the data-center accelerator training the model you are probably using right now.

Engineers new to the field usually ask a version of the wrong question: which one is best? There is no winner. AMBA is a layered toolkit, and the real skill — the thing interviewers probe and senior designers internalize — is knowing why each bus exists and matching each block to the bus sized for its traffic. This guide is the complete reference on that decision: the history, the architecture, the timing, the RTL, the verification implications, the trade-offs in area, power, and timing closure, and the interview questions that separate people who memorized signal names from people who understand the protocols.

1. Introduction — why this comparison matters

Every SoC is an exercise in heterogeneous integration: a CPU cluster running at gigahertz sits on the same die as a UART that dribbles out bytes at 115,200 baud. If you wired both with the same interconnect, one of two bad things happens. Either you give the UART a full high-performance interface — burning gate area, routing congestion, dynamic power, and weeks of verification on a block that needs none of it — or you throttle the CPU down to the peripheral's simplicity and strangle system bandwidth. AMBA's answer is to define a family where each member trades complexity for throughput at a different operating point, and to let bridges stitch the tiers together.

Understanding AXI, AHB, and APB well pays off in three concrete ways:

• RTL design. You choose the right interface for each block and avoid the classic mistake of over- or under-provisioning a bus.
• Verification. You size the testbench and coverage model to the protocol's real corner cases — trivial for APB, substantial for AXI.
• Interviews. "Explain the difference between AXI, AHB, and APB" is one of the most common front-end and verification interview questions in the industry, and the depth of your answer is a direct signal of your seniority.

2. A short history of AMBA

AMBA was introduced by Arm (then Advanced RISC Machines) in 1996 to standardize how blocks talk inside a chip so that IP could be reused across designs instead of re-glued every time. The first generation defined the ASB (Advanced System Bus) and APB (Advanced Peripheral Bus). ASB was quickly superseded, but APB survived essentially unchanged in spirit for nearly thirty years — proof that a protocol built for the right job at the right complexity ages extremely well.

The pressure that drove every later generation was the same: bandwidth demand grew faster than the previous bus could serve it, while the need for cheap peripheral access never went away. Rather than replace the whole family each time, Arm added capability at the top and kept the simpler members underneath. That is why a 2026 SoC still contains all three classic buses at once.

3. The evolution of AMBA

The lineage, generation by generation:

• AMBA (1996) — ASB and APB. First attempt at a reusable on-chip standard.
• AMBA 2 (1999) — AHB and APB2. AHB introduced pipelining and bursts on a shared multi-master bus; APB2 tidied the peripheral bus.
• AMBA 3 (2003) — AXI3, AHB-Lite, APB3. AXI3 brought the five-channel, outstanding-transaction model. AHB-Lite simplified AHB to a single master (dropping the arbiter) for the common case. APB3 added PREADY (wait states) and PSLVERR (error reporting).
• AMBA 4 (2010) — AXI4, AXI4-Lite, AXI4-Stream, ACE. AXI4 extended bursts to 256 beats and refined the spec; AXI4-Lite gave a simple register-access subset; AXI4-Stream added address-less data streaming; ACE (AXI Coherency Extensions) added hardware cache coherency. APB4 added PPROT and PSTRB.
• AMBA 5 (2013 onward) — CHI (Coherent Hub Interface), plus ACE5 and AXI5. CHI is a packet-based, scalable, coherent interconnect for many-core and server-class designs where a shared bus no longer scales.

4. Why multiple buses exist

The deep reason is an economics-of-silicon argument, and it is worth stating precisely because it is the spine of every design decision in this article.

A bus interface costs gate area (registers, muxes, decoders, FSMs), wires (hundreds of signals for AXI versus a few dozen for APB, which drives routing congestion and power), dynamic power (every toggling wire and flop), and verification effort (the corner-case space you must close before tapeout). These costs are justified only when the block's traffic actually needs the capability they buy.

• A DDR controller feeding a CPU cluster needs to keep hundreds of bytes in flight to hide 100-plus-nanosecond DRAM latency. Only AXI's outstanding transactions and bursts make that possible. The cost is worth it.
• A GPIO block needs a handful of register writes per millisecond. It needs none of AXI's machinery. Putting it on AXI is like building a freeway on-ramp to a mailbox.

So the family exists because one operating point cannot be optimal for all traffic. The engineering act is partitioning the SoC into tiers and matching each block to the cheapest bus that meets its bandwidth, latency, and concurrency needs. For the deeper rationale of each bus individually, see why APB exists, why AHB exists, and why AXI exists.

5. Architecture comparison at a glance

Before the deep dives, here is the structural contrast that everything else follows from.

The rest of this guide unpacks each row and shows the hardware, timing, and RTL that make it true.

6. APB deep dive

APB — the Advanced Peripheral Bus — is the control plane of the SoC. Its entire design philosophy is that most peripherals do not need bandwidth; they need cheap, predictable, easily verified register access.

6.1 The APB signal set

6.2 The two-phase transfer and the APB state machine

Every APB transfer is exactly two phases. In the SETUP phase the master asserts PSEL, drives PADDR, PWRITE, and (for writes) PWDATA, and holds PENABLE low — giving the slave one full cycle to decode. In the ACCESS phase the master raises PENABLE; the transfer completes on the first cycle the slave drives PREADY high. If PREADY is low, the access is held in wait states.

Here is the same write as an interactive-style waveform using the platform's protocol preset:

A read is identical except PWRITE is low and the slave drives PRDATA during the access phase:

And a slow slave inserting wait states simply holds PREADY low:

6.3 Production-quality APB slave RTL

A minimal, synthesizable APB3 slave with three registers and correct wait-state and error behavior:

// Simple APB3 slave: 3 x 32-bit registers, one wait state on writes.
module apb_slave #(
  parameter int ADDR_W = 8,
  parameter int DATA_W = 32
)(
  input  logic              pclk,
  input  logic              presetn,
  input  logic              psel,
  input  logic              penable,
  input  logic              pwrite,
  input  logic [ADDR_W-1:0] paddr,
  input  logic [DATA_W-1:0] pwdata,
  output logic [DATA_W-1:0] prdata,
  output logic              pready,
  output logic              pslverr
);
  // Word-aligned register offsets (byte address, low 2 bits ignored).
  localparam CTRL   = 8'h00;
  localparam STATUS = 8'h04;
  localparam DATA   = 8'h08;
 
  logic [DATA_W-1:0] ctrl_q, data_q;
  logic [DATA_W-1:0] status_q;
 
  // "access phase" is asserted when psel & penable are both high.
  wire access = psel & penable;
 
  // Decode a legal, mapped, word-aligned offset.
  wire addr_ok = (paddr[1:0] == 2'b00) &&
                 (paddr[ADDR_W-1:2] == CTRL[ADDR_W-1:2]  ||
                  paddr[ADDR_W-1:2] == STATUS[ADDR_W-1:2] ||
                  paddr[ADDR_W-1:2] == DATA[ADDR_W-1:2]);
 
  // One wait state: pready deasserts on the first access cycle, asserts next.
  logic ready_q;
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn)      ready_q <= 1'b0;
    else if (access)   ready_q <= ~ready_q;   // 0 -> 1 across the access
    else               ready_q <= 1'b0;
  end
  assign pready  = ready_q;                    // completes on the 2nd access cycle
  assign pslverr = access & pready & ~addr_ok; // error only on the completion edge
 
  // Write on the completion edge of a legal write.
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      ctrl_q <= '0; data_q <= '0;
    end else if (access && pready && pwrite && addr_ok) begin
      case (paddr[ADDR_W-1:0])
        CTRL: ctrl_q <= pwdata;
        DATA: data_q <= pwdata;
        default: ;                             // STATUS is read-only
      endcase
    end
  end
 
  // Combinational read mux.
  always_comb begin
    unique case (paddr[ADDR_W-1:0])
      CTRL:    prdata = ctrl_q;
      STATUS:  prdata = status_q;
      DATA:    prdata = data_q;
      default: prdata = '0;
    endcase
  end
endmodule

Hardware generated: three 32-bit register banks, a small equality decoder, a read mux, and a single toggle flop for the wait state. Synthesis implications: the whole block is a handful of flops and muxes — a few hundred gates — with relaxed timing because there is no pipeline. Verification considerations: the corner cases are few and well-bounded — write-then-read coherence, the wait-state cycle, error on an unmapped address, and reset-during-access. This is why APB testbenches close quickly. The mental model behind this register interface is covered in the APB register-access model, and the PREADY handshake in depth in the PREADY ready handshake tutorial.

6.4 APB master FSM RTL

The other side of the wire — a compact APB master that drives the two-phase sequence and honors wait states:

// APB3 master: drives IDLE -> SETUP -> ACCESS, honoring PREADY wait states.
module apb_master #(parameter int AW=8, DW=32)(
  input  logic          pclk, presetn,
  // command interface from the core
  input  logic          req,     // pulse to start a transfer
  input  logic          wr,      // 1=write 0=read
  input  logic [AW-1:0] addr,
  input  logic [DW-1:0] wdata,
  output logic          done,    // 1-cycle pulse on completion
  output logic [DW-1:0] rdata,
  output logic          err,
  // APB port
  output logic          psel, penable, pwrite,
  output logic [AW-1:0] paddr,
  output logic [DW-1:0] pwdata,
  input  logic [DW-1:0] prdata,
  input  logic          pready, pslverr
);
  typedef enum logic [1:0] {IDLE, SETUP, ACCESS} st_e;
  st_e st;
 
  always_ff @(posedge pclk or negedge presetn) begin
    if (!presetn) begin
      st<=IDLE; psel<=0; penable<=0; pwrite<=0;
      paddr<='0; pwdata<='0; done<=0; rdata<='0; err<=0;
    end else begin
      done <= 1'b0;                        // default: no completion
      case (st)
        IDLE: if (req) begin
                psel<=1'b1; penable<=1'b0; // SETUP phase begins
                pwrite<=wr; paddr<=addr; pwdata<=wdata;
                st<=SETUP;
              end
        SETUP: begin penable<=1'b1; st<=ACCESS; end   // enter ACCESS
        ACCESS: if (pready) begin           // completes only when PREADY high
                  psel<=1'b0; penable<=1'b0;
                  rdata<=prdata; err<=pslverr; done<=1'b1;
                  st<=IDLE;
                end                          // else hold — wait state
      endcase
    end
  end
endmodule

Hardware generated: a 2-bit state register, command-hold registers, and the APB output drivers. Synthesis implications: tiny and timing-relaxed; the only care is that PADDR/PWDATA/PWRITE stay stable from SETUP through completion (the FSM holds them, which is the protocol requirement). Verification considerations: cover zero-wait and multi-wait slaves, back-to-back requests, reads returning PRDATA only on the completion edge, and PSLVERR capture.

7. AHB deep dive

AHB — the Advanced High-performance Bus — is the middle tier: a pipelined, shared, multi-master backbone for on-chip memory and moderate-bandwidth traffic.

7.1 Key AHB signals

7.2 Pipelining — the core AHB idea

AHB overlaps the address phase of one transfer with the data phase of the previous one. While the data of transfer N moves on HWDATA/HRDATA, the address of transfer N+1 is already presented on HADDR. At steady state this yields roughly one transfer per cycle — a large improvement over APB's strictly serial two phases.

7.3 Bursts and the transfer-type sequence

An AHB burst issues one address handshake per beat, with HTRANS going NONSEQ on the first beat and SEQ on each following beat, while HADDR increments by the transfer size. HBURST tells slaves and arbiters how long the burst is so they can optimize (and so the arbiter can avoid breaking it up unnecessarily).

A slave that needs more time simply holds HREADY low, stretching the current data phase and stalling the whole pipeline behind it:

Bursts are covered end-to-end in the AHB burst overview and INCR bursts; the HREADY mechanics are in the HREADY meaning tutorial.

7.4 Arbitration — the price of a shared bus

Because AHB is shared, multiple masters (CPU, DMA, bridge) may want it simultaneously. An arbiter grants the bus to one master per transfer. The two canonical schemes:

• Fixed priority — simple, but low-priority masters can starve. See fixed-priority arbitration.
• Round robin — fair rotation, no starvation, slightly more logic. See round-robin arbitration.

Arbitration is a real cost: it adds a request/grant handshake, forces a decision every transfer, and can fragment bursts if not designed to lock them. The full rationale is in why arbitration exists. This shared-bus arbitration is precisely the bottleneck AXI removes by giving every master its own point-to-point channels through an interconnect.

7.5 AHB burst-writer RTL sketch

// AHB-Lite master fragment: issue a 4-beat INCR4 write burst.
// Shows the NONSEQ -> SEQ transfer-type sequence and address increment.
typedef enum logic [1:0] {IDLE=2'b00, BUSY=2'b01, NONSEQ=2'b10, SEQ=2'b11} htrans_e;
 
module ahb_burst_writer #(parameter int AW=32, DW=32)(
  input  logic          hclk, hresetn, hready,
  output logic [AW-1:0] haddr,
  output htrans_e       htrans,
  output logic          hwrite,
  output logic [2:0]    hburst,
  output logic [DW-1:0] hwdata,
  input  logic          start,
  input  logic [AW-1:0] base
);
  logic [2:0] beat;                 // 0..3
  logic       active;
 
  always_ff @(posedge hclk or negedge hresetn) begin
    if (!hresetn) begin
      active <= 1'b0; beat <= '0; haddr <= '0;
      htrans <= IDLE; hwrite <= 1'b0; hburst <= 3'b000;
    end else if (hready) begin       // advance only when the bus is ready
      if (start && !active) begin
        active <= 1'b1; beat <= 3'd0;
        haddr  <= base;  htrans <= NONSEQ;      // first beat
        hwrite <= 1'b1;  hburst <= 3'b011;      // INCR4
      end else if (active) begin
        if (beat == 3'd3) begin
          active <= 1'b0; htrans <= IDLE;       // burst done
        end else begin
          beat  <= beat + 3'd1;
          haddr <= haddr + (AW/8);              // +4 for 32-bit
          htrans<= SEQ;                          // remaining beats
        end
      end
    end
  end
  assign hwdata = {29'd0, beat};    // placeholder payload
endmodule

Hardware generated: a small burst counter, an address incrementer, and the transfer-type FSM. Synthesis implications: the address incrementer and the HREADY-gated advance sit on the bus critical path; in a real design HRDATA/HWDATA muxing across many slaves is often the timing-closure hotspot. Verification considerations: you must cover burst boundaries, HREADY stalls mid-burst, BUSY insertion, early burst termination, and HRESP=ERROR handling — materially more than APB. The single-versus-burst distinction is explored in single vs burst transfer.

8. AXI deep dive

AXI — the Advanced eXtensible Interface — is the high-performance tier. Its defining idea is decoupling: it splits a transaction into five independent channels, each with its own VALID/READY handshake, so address, data, and response flow concurrently and many transactions can be in flight at once.

8.1 The five channels

The five channels are:

• AW — Write Address: AWADDR, AWLEN (burst length), AWSIZE, AWBURST, AWID.
• W — Write Data: WDATA, WSTRB (byte strobes), WLAST.
• B — Write Response: BRESP (OKAY/SLVERR/DECERR), BID.
• AR — Read Address: ARADDR, ARLEN, ARSIZE, ARBURST, ARID.
• R — Read Data: RDATA, RRESP, RLAST, RID.

See the channel breakdown in the five-channels tutorial and the handshake itself in the AXI VALID/READY handshake.

8.2 The VALID/READY handshake

Every AXI channel uses the same rule: a beat transfers on a rising clock edge when both VALID and READY are high. The source raises VALID when it has information; the destination raises READY when it can accept. Either side can wait for the other, which is how AXI implements flow control and back-pressure without a separate protocol.

Back-pressure in a real AXI burst — the slave throttling the master by dropping READY:

The canonical building block that makes VALID/READY safe to pipeline is the skid buffer — a two-entry register slice that breaks timing paths on VALID, READY, and data without ever dropping a beat:

// AXI-style valid/ready skid buffer (register slice). Fully pipelined,
// no combinational path from s_ready back to s_valid.
module axi_skid #(parameter int W=32)(
  input  logic         clk, rstn,
  // upstream (slave port)
  input  logic         s_valid, input  logic [W-1:0] s_data,
  output logic         s_ready,
  // downstream (master port)
  output logic         m_valid, output logic [W-1:0] m_data,
  input  logic         m_ready
);
  logic         full;      // skid register occupied
  logic [W-1:0] skid;
 
  assign s_ready = !full;                 // accept while the skid slot is free
  assign m_valid = full ? 1'b1 : s_valid; // present skid, else pass-through
  assign m_data  = full ? skid  : s_data;
 
  always_ff @(posedge clk or negedge rstn) begin
    if (!rstn) begin
      full <= 1'b0; skid <= '0;
    end else begin
      if (!full && s_valid && !m_ready) begin
        full <= 1'b1; skid <= s_data;     // downstream stalled -> capture
      end else if (full && m_ready) begin
        full <= 1'b0;                     // downstream drained the skid slot
      end
    end
  end
endmodule

Hardware generated: one data register plus a single occupancy flop. Synthesis implications: this is the standard way to close timing on an AXI channel — dropping a skid slice on AW/W/AR/R cuts the long crossbar paths at the cost of one cycle of latency, with zero throughput loss. Verification considerations: prove no beat is ever dropped or duplicated under arbitrary VALID/READY stall patterns; a formal check of the two-entry invariant is standard.

8.3 Write and read transaction flow

8.4 Outstanding transactions and out-of-order completion

This is AXI's superpower. A master may issue many addresses before earlier transactions complete — these are outstanding transactions. Because each carries an ID, transactions with different IDs may complete out of order: a fast slave can answer before a slow slave that was addressed earlier. The master re-associates each response to its request using the returned BID/RID.

This is exactly why AXI sustains DRAM bandwidth: while the memory controller works on request 1, requests 2, 3, and 4 are already queued. APB and AHB, with one transfer in flight, would idle waiting for each response.

8.5 AXI-Lite write FSM RTL

A compact AXI4-Lite write channel handler for a register block — the common way to give a control block an AXI-style interface without full-AXI complexity:

// AXI4-Lite write path: AW + W -> B. Single beat, no bursts, no IDs.
module axilite_wr #(parameter int AW=12, DW=32)(
  input  logic          aclk, aresetn,
  // AW channel
  input  logic [AW-1:0] awaddr,  input logic awvalid, output logic awready,
  // W channel
  input  logic [DW-1:0] wdata,   input logic [DW/8-1:0] wstrb,
  input  logic          wvalid,  output logic wready,
  // B channel
  output logic [1:0]    bresp,   output logic bvalid, input logic bready
);
  typedef enum logic [1:0] {W_IDLE, W_DATA, W_RESP} state_e;
  state_e state;
  logic [AW-1:0] addr_q;
 
  always_ff @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      state <= W_IDLE; awready <= 1'b0; wready <= 1'b0;
      bvalid <= 1'b0;  bresp <= 2'b00; addr_q <= '0;
    end else begin
      case (state)
        W_IDLE: begin
          awready <= 1'b1;                       // accept an address
          if (awvalid && awready) begin
            addr_q  <= awaddr; awready <= 1'b0;
            wready  <= 1'b1;   state   <= W_DATA; // now accept data
          end
        end
        W_DATA: begin
          if (wvalid && wready) begin
            wready <= 1'b0;
            // ... commit wdata/wstrb to the register at addr_q here ...
            bresp  <= 2'b00;   bvalid <= 1'b1;    // OKAY response
            state  <= W_RESP;
          end
        end
        W_RESP: begin
          if (bvalid && bready) begin             // response accepted
            bvalid <= 1'b0; awready <= 1'b1; state <= W_IDLE;
          end
        end
      endcase
    end
  end
endmodule

Hardware generated: a three-state FSM, one address-hold register, and the response flop. Synthesis implications: trivial logic, but note the FSM deliberately accepts address then data then emits response — a full-AXI slave would instead allow AW and W to arrive in either order and support multiple outstanding IDs, which costs FIFOs and ID-tracking logic. Verification considerations: even this simple case must handle AW/W arriving in any relative order, BREADY back-pressure, and byte-strobe masking. Register access over AXI4-Lite is covered in AXI4-Lite register access; the read and write paths in the read path and the write path; channel independence in independent channels.

8.6 AXI read FSM RTL

The read side — an AXI4-Lite-style read handler that accepts an address on AR and streams the response on R (extend rlast/a beat counter for full-AXI bursts):

// AXI read path: AR -> R. Single-beat (AXI4-Lite); add a beat counter for bursts.
module axi_rd #(parameter int AW=12, DW=32)(
  input  logic          aclk, aresetn,
  // AR channel
  input  logic [AW-1:0] araddr, input logic arvalid, output logic arready,
  // R channel
  output logic [DW-1:0] rdata,  output logic [1:0] rresp,
  output logic          rvalid, input  logic rready
);
  typedef enum logic [1:0] {R_IDLE, R_DATA} state_e;
  state_e state;
  logic [AW-1:0] addr_q;
 
  always_ff @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      state<=R_IDLE; arready<=1'b0; rvalid<=1'b0; rresp<=2'b00; rdata<='0;
    end else begin
      case (state)
        R_IDLE: begin
          arready <= 1'b1;                       // ready to accept an address
          if (arvalid && arready) begin
            addr_q  <= araddr; arready <= 1'b0;
            // ... fetch register/memory at araddr into rdata ...
            rdata   <= {20'd0, araddr};           // placeholder read data
            rresp   <= 2'b00;                      // OKAY
            rvalid  <= 1'b1; state <= R_DATA;
          end
        end
        R_DATA: if (rvalid && rready) begin        // master accepted the data
          rvalid <= 1'b0; state <= R_IDLE;
        end
      endcase
    end
  end
endmodule

Hardware generated: a two-state FSM, an address-hold register, and the read-data drivers. Synthesis implications: trivial; a full-AXI read adds a beat counter, RLAST generation, and per-ID response FIFOs to support outstanding, out-of-order reads. Verification considerations: cover RREADY back-pressure, address/data ordering, error responses (SLVERR/DECERR), and — for the burst version — correct RLAST on exactly the final beat.

9. Head-to-head: the engineering trade-offs

The following sections compare the three buses along the axes that actually drive design decisions.

9.1 Pipeline comparison

• APB: no pipeline. SETUP and ACCESS are serial; a transfer is at least two cycles.
• AHB: one pipeline stage — address phase overlaps the previous data phase, so steady-state throughput approaches one transfer per cycle.
• AXI: deep, per-channel pipelining plus independent channels; address, data, and response for different transactions all move simultaneously.

9.2 Burst comparison

A crucial structural difference: AHB issues one address per beat; AXI issues one address for the entire burst and streams the data beats. That alone makes AXI far more address-efficient for long transfers.

9.3 Arbitration comparison

• APB: no arbitration — a single master (or a bridge acting as the single master).
• AHB: explicit central arbiter; request/grant per transfer; fixed-priority or round-robin; risk of starvation or burst fragmentation.
• AXI: no shared-bus arbiter in the AHB sense; arbitration is distributed inside the interconnect, which routes point-to-point and can serve multiple master/slave pairs concurrently.

9.4 Outstanding transactions and ordering

Ordering is subtle and interview-relevant: AXI guarantees ordering within the same ID, but transactions with different IDs may complete in any order. This is the lever that lets AXI hide latency without violating a master's assumptions.

9.5 Latency

For a single isolated access, APB and AHB can actually have lower latency than AXI because AXI's channel handshakes and interconnect add pipeline stages. AXI wins on throughput under load, not single-shot latency. This nuance is exactly what separates a memorized answer from an understood one.

9.6 Bandwidth

Peak bandwidth scales with data width times clock times useful-beats-per-cycle. AXI's wide data paths (up to 1024 bits), long bursts, and outstanding transactions let it sustain near-peak bandwidth to memory; AHB sustains roughly one beat per cycle on a shared path; APB is not a bandwidth device at all.

9.7 Power

More capability means more toggling logic and wires, so dynamic power tracks complexity: AXI > AHB > APB per transaction of infrastructure. But energy per useful byte moved can favor AXI for bulk data because it moves so much per transaction and idles cleanly between bursts. For control traffic, APB is dramatically lower power — another reason peripherals stay on it.

9.8 Area

Gate area follows the same order: an AXI interface (with ID tracking, outstanding- transaction FIFOs, and five channels) can be an order of magnitude larger than an APB slave. On a chip with dozens of peripherals, keeping them on APB instead of AXI saves real silicon.

9.9 Complexity and verification effort

This is why an AXI VIP is a major piece of IP while an APB agent is a weekend project.

9.10 Timing closure

• APB is the friendliest to close — combinational decode off a stable address, no pipeline, relaxed paths.
• AHB puts the address incrementer, the slave-select decode, and the HRDATA mux on the critical path; wide multi-slave HRDATA muxes are a common closure headache.
• AXI distributes timing across channels (good) but the interconnect crossbar, ID tracking, and wide data muxes create their own closure challenges, usually solved with register slices on the channels.

10. The complete protocol comparison table

11. Real SoC architecture — putting it together

On a real chip the three buses are layered, not chosen as one winner. AXI forms the data-plane backbone, AHB serves mid-bandwidth on-chip memory, and APB carries the control plane, with bridges joining the tiers.

11.1 Where each protocol is used

• AXI — application-processor clusters, GPUs and neural accelerators, DMA engines, high-bandwidth on-chip SRAM, and the DDR/LPDDR memory controller.
• AHB / AHB-Lite — boot ROM, tightly-coupled memory, on-chip SRAM in microcontrollers, and mid-bandwidth blocks that don't justify AXI.
• APB — UART, SPI, I²C, GPIO, timers, watchdog, PWM, PLL/clock and reset control, eFuse — the long tail of configuration-register blocks.

11.2 CPU example

A CPU rarely touches the bus directly for data — its caches do. On a miss, the L2 cache fetches an entire cache line as an AXI INCR burst (for example four 64-bit beats for a 32-byte line), and evicts dirty lines as write bursts. The cache issues multiple outstanding line fills to hide DRAM latency — the exact workload AXI was designed for.

11.3 DMA example

A DMA engine is the clearest illustration of the control-plane/data-plane split. The CPU configures it over APB — source address, destination address, length, and a start bit — a few small register writes. The DMA then moves the data over AXI using independent read and write master ports, streaming bursts with many outstanding transactions, entirely without the CPU. Control on APB, bulk data on AXI: the whole AMBA philosophy in one block.

11.4 Memory-controller example

The DDR/LPDDR controller is AXI's most demanding client. DRAM latency is high and bank/row management rewards reordering, so the controller relies on AXI's many outstanding transactions to keep its command pipeline full and on out-of-order completion to return data as banks become ready. Nothing less than AXI can keep a modern memory system near its bandwidth ceiling.

12. Bridge architecture and protocol conversion

Because the tiers use different protocols, bridges translate between them. A bridge is a dual-personality block: a slave on the upstream (faster) side and a master on the downstream (slower) side.

A bridge must handle four cross-boundary concerns:

1. Rate and serialisation. One upstream AXI burst becomes N single APB transfers, so the bridge stalls the upstream channels (via AWREADY/WREADY/ARREADY) while it drains each APB access. An unbounded APB wait becomes an unbounded upstream stall, which is why robust bridges carry a completion watchdog.
2. Error mapping. APB PSLVERR must become AXI BRESP/RRESP = SLVERR, accumulated (sticky-OR) across a burst into a single response — never dropped, never invented.
3. Ordering. A burst serialises to N APB singles in address order; the bridge must preserve it.
4. Clock-domain crossing. The bridge often sits on the boundary between a fast fabric clock and a slow PCLK, so the request/response handshake must be synchronised (never the raw multi-bit bus).

The bridge internals — address mapping and the FSM — are covered in the AXI-to-APB bridge tutorial and bridge FSM design.

// AXI-Lite-to-APB bridge skeleton: one AXI-Lite access -> one APB transfer.
// (Write path shown; read path is symmetric with AR/R and PRDATA.)
module axil2apb_wr #(parameter int AW=12, DW=32)(
  input  logic          clk, rstn,
  // AXI-Lite write in
  input  logic [AW-1:0] awaddr, input logic awvalid, output logic awready,
  input  logic [DW-1:0] wdata,  input logic wvalid,  output logic wready,
  output logic [1:0]    bresp,  output logic bvalid, input  logic bready,
  // APB manager out
  output logic          psel, penable, pwrite,
  output logic [AW-1:0] paddr,
  output logic [DW-1:0] pwdata,
  input  logic [DW-1:0] prdata,
  input  logic          pready, pslverr
);
  typedef enum logic [1:0] {IDLE, SETUP, ACCESS, RESP} st_e;
  st_e st;
 
  always_ff @(posedge clk or negedge rstn) begin
    if (!rstn) begin
      st <= IDLE; psel<=0; penable<=0; pwrite<=0;
      awready<=0; wready<=0; bvalid<=0; bresp<=2'b00;
      paddr<='0; pwdata<='0;
    end else begin
      awready<=0; wready<=0;
      case (st)
        IDLE: if (awvalid && wvalid) begin       // wait for addr AND data
                 paddr<=awaddr; pwdata<=wdata; pwrite<=1'b1;
                 awready<=1'b1; wready<=1'b1;     // accept both
                 psel<=1'b1; penable<=1'b0; st<=SETUP;   // APB SETUP
               end
        SETUP: begin penable<=1'b1; st<=ACCESS; end       // APB ACCESS
        ACCESS: if (pready) begin                          // wait states honored
                  psel<=1'b0; penable<=1'b0;
                  bresp<= pslverr ? 2'b10 : 2'b00;         // SLVERR : OKAY
                  bvalid<=1'b1; st<=RESP;
                end
        RESP: if (bready) begin bvalid<=1'b0; st<=IDLE; end
      endcase
    end
  end
endmodule

Hardware generated: the APB two-phase FSM, address/data holding registers, and the error-mapping mux. Synthesis implications: small, but the CDC synchronisers (omitted here for clarity) and the watchdog are essential in a real multi-clock design. Verification considerations: cover APB wait states of varying length, PSLVERR mapping, back-to-back accesses, reset mid-transfer, and — critically — that upstream is correctly stalled and never deadlocks.

13. Common mistakes engineers make

14. Interview questions with answers

Thirty questions, from fundamentals to senior-level system reasoning. Try to answer each before reading the response.

Beginner

Q1. What does AMBA stand for, and name its three classic buses. Advanced Microcontroller Bus Architecture. The three classic buses are APB, AHB, and AXI.

Q2. What is APB used for? Low-speed peripheral register access — UART, GPIO, timers, SPI, I²C — where simplicity and small area matter more than bandwidth.

Q3. How many phases does an APB transfer have, and what are they? Two: SETUP (PSEL high, PENABLE low, address presented) and ACCESS (PENABLE high, completes when PREADY is high).

Q4. What does PREADY do? It is the slave's ready signal; while low during ACCESS it inserts wait states, and the transfer commits on the cycle it is high.

Q5. How many channels does AXI have and what are they? Five: AW, W, B (write) and AR, R (read).

Q6. What is the AXI handshake rule? A beat transfers when both VALID and READY are high on a rising clock edge.

Q7. Does APB support bursts? No — one transfer at a time.

Q8. What is HTRANS in AHB? The transfer-type signal: IDLE, BUSY, NONSEQ, SEQ. NONSEQ starts a burst; SEQ continues it.

Q9. Which bus would you use for a DDR controller, and which for a GPIO block? AXI for the DDR controller (bandwidth, latency hiding); APB for the GPIO (simple register access).

Q10. What does a bridge do? Translates between two protocols/tiers — for example an AXI-to-APB bridge is an AXI slave on one side and an APB master on the other.

Intermediate

Q11. Why is AHB faster than APB? AHB pipelines address and data phases (overlapping consecutive transfers) and supports bursts, approaching one transfer per cycle, whereas APB is strictly two serial phases per transfer.

Q12. What is an outstanding transaction? One whose address is accepted but whose data/response has not yet returned; AXI allows many, APB and AHB allow one.

Q13. Explain out-of-order completion in AXI. Transactions carry IDs; those with different IDs may complete in any order, and the master matches responses to requests by BID/RID. Order is preserved within a single ID.

Q14. What is the difference between AXI4 and AXI4-Lite? AXI4-Lite is a single-beat, no-burst, no-ID subset for simple register access; AXI4 has bursts up to 256 beats and IDs.

Q15. What is AXI4-Stream for? Unidirectional, address-less data streaming — video, DSP, packets — point to point.

Q16. How does AHB arbitration work and what can go wrong? A central arbiter grants the shared bus per transfer (fixed-priority or round-robin); fixed priority can starve low-priority masters, and careless arbitration can fragment bursts.

Q17. What do WLAST and RLAST signal? The final beat of a write-data and read-data burst respectively.

Q18. What is WSTRB? Per-byte write strobes that select which byte lanes of WDATA are actually written, enabling partial (sub-word) writes.

Q19. Why can a single AXI read return multiple data beats from one address? Because ARLEN specifies a burst; one AR handshake requests ARLEN+1 beats, streamed on R.

Q20. In an AHB burst, how often is the address issued? Once per beat (with HADDR incrementing), unlike AXI which issues one address for the whole burst.

Senior / system-level

Q21. A read is issued right after a write to the same address on AXI with different IDs. Is the read guaranteed to see the write? No. Different IDs impose no ordering; you must use the same ID or an explicit synchronisation/barrier to guarantee the read observes the write.

Q22. Why does AXI hide memory latency but AHB cannot? AXI keeps many transactions outstanding, so the memory controller always has work queued; AHB has one transfer in flight and stalls waiting for each response.

Q23. Where does an AXI-to-APB bridge risk deadlock, and how do you prevent it? If an APB slave never asserts PREADY, the bridge stalls upstream indefinitely. Prevent it with a bounded completion watchdog and correct back-pressure that never blocks a required response channel.

Q24. How is an APB PSLVERR in the middle of a bridged AXI burst reported upstream? It is mapped to SLVERR and sticky-OR-accumulated across the burst into the single BRESP (writes) or per-beat RRESP (reads) — never dropped, never fabricated.

Q25. What are the timing-closure hotspots on each bus? APB: relaxed. AHB: the HRDATA multi-slave mux and address incrementer. AXI: the interconnect crossbar and wide data muxes, usually mitigated with channel register slices.

Q26. Why might a single isolated AXI access have higher latency than APB? AXI's per-channel handshakes and interconnect pipeline add stages; AXI's advantage is throughput under load, not single-shot latency.

Q27. How would you size verification effort across the three? APB: light directed plus assertions. AHB: constrained-random with arbitration/burst coverage. AXI: full UVM VIP covering interleaving, outstanding depth, ordering, exclusive access, and error responses.

Q28. What is the purpose of transaction IDs beyond reordering? They allow multiple independent streams to share an interface without head-of-line blocking, and let the interconnect route and track concurrent transactions.

Q29. Why keep AHB in a modern AXI-based SoC at all? For on-chip SRAM/ROM and mid-bandwidth blocks, AHB-Lite is cheaper in area, power, and verification than AXI while still offering bursts and pipelining.

Q30. Describe the control-plane vs data-plane split using DMA. The CPU configures the DMA via a few APB register writes (control plane); the DMA moves bulk data over AXI with bursts and outstanding transactions (data plane) — cheap control, high-throughput data.

15. Related tutorials

To go from this overview into signal-level depth, follow the curriculum:

• APB: why APB exists · register-access model · PREADY handshake
• AHB: why AHB exists · burst overview · why arbitration · HREADY meaning
• AXI: why AXI exists · five channels · VALID/READY handshake · AXI4-Lite register access
• Bridges: AXI-to-APB bridge · bridge FSM design

16. Summary

AMBA is not one bus but a layered family, and choosing correctly is a per-block engineering decision, not a search for a single best protocol:

• APB — the control plane. Two-phase, unpipelined, single-transfer, tiny, trivial to verify. Use it for every slow register block.
• AHB — the mid tier. Pipelined, shared, multi-master, bursts. Use it for on-chip memory and moderate-bandwidth blocks that don't justify AXI.
• AXI — the data-plane backbone. Five decoupled channels, long bursts, many outstanding out-of-order transactions. Use it for CPUs, GPUs, DMA, and memory.

The senior insight to carry into your next design review or interview: the traffic chooses the bus, not a preference for the newest or fastest one. A real chip runs all three at once — freeway, avenue, and side street — each matched to the load it carries, stitched together by bridges. Master that partitioning, and you understand not just three protocols but the architecture of the modern SoC.

If you found this useful, the companion piece why APB still matters in an AXI world approaches the same decision from a complementary angle.