AMBA APB · Module 3

PREADY — The Ready Handshake

PREADY, the subordinate's one lever over timing — how holding it low stretches the access phase (backpressure) and driving it high completes the transfer, all on the same lifecycle.

Module 2 named PREADY as the lifecycle's "completion-and-backpressure control" — the thing that ends the access phase or holds it. That is the right role, but to drive PREADY from a real subordinate, or sample it in a real manager, you need its exact contract: who drives it, what high means, what low means, and the rule that makes a trivial register correct. PREADY is the subordinate's one and only lever over transfer timing — high says "this access is done now," low inserts a wait state that stretches the access phase. The single idea to carry: PREADY is subordinate-driven, sampled by the manager during the access phase, and a transfer completes on the one cycle it is high — never a cycle sooner.

1. What problem is being solved?

The problem is letting subordinates of wildly different speeds share one bus, while giving the manager one unambiguous cycle on which every transfer finishes.

A single APB bus hosts a plain configuration register that answers instantly, a register in a slower clock domain, and a bridge to another slow bus that needs several cycles to settle. The manager cannot know in advance how long each will take. APB solves this with a single subordinate-driven ready bit:

PREADY high says the subordinate is ready: the access completes on this cycle — a write is captured, read data is valid.
PREADY low says the subordinate is not ready yet: hold the access, insert a wait state, and ask again next cycle.

That one bit is the whole mechanism that makes the access phase elastic. Without it, APB would have to fix every access at a single latency — forcing every subordinate to the worst case, or forbidding slow ones outright. PREADY is what lets a one-cycle register and a ten-cycle bridge live on the same wires.

2. Why the lifecycle view is not enough

Module 2 told you PREADY is the completion-and-backpressure control — a lifecycle role. That is true, but a role is not a contract. To wire PREADY into a real subordinate or check it in a manager, the lifecycle view leaves three things unstated:

Who drives it, and when it is sampled. PREADY is driven by the subordinate, and the manager samples it during the access phase (PENABLE high). A manager never drives PREADY; a subordinate never reads it to decide its own behaviour. It is a one-way signal from subordinate to manager.
High means "complete now," not "I am alive." PREADY high on an access cycle is the completion edge — the cycle the transfer ends. It is not a status flag the subordinate leaves asserted; it is the subordinate's per-transfer "done."
Low is the only backpressure APB has. Holding PREADY low is the subordinate's single tool for affecting timing. There is no other wait mechanism, no separate "busy" line. The phase stretches purely because PREADY is low and the manager keeps everything stable while it waits.

Knowing the role tells you what PREADY means; knowing the contract tells you what PREADY looks like on the wire and who owns it — which is what you actually need to build or debug a stretched transfer.

3. The signal's mental model

The model: PREADY is the subordinate's hand raised to say "done" — and lowered to say "wait."

Picture a transaction at a counter. The form is on the counter and you are standing there with PENABLE high. The clerk (the subordinate) controls one thing: whether to stamp now or make you wait. A raised hand with the stamp coming down is PREADY high — the transaction is done this instant. A lowered hand is PREADY low — keep the form on the counter, nothing changes hands, ask again next beat. You, the manager, do not get to stamp; you only watch the clerk's hand and keep the form steady until it comes down.

Three refinements make the model precise:

Only the subordinate's hand moves. PREADY is driven solely by the subordinate. The manager samples it during the access phase and reacts; it never asserts PREADY itself. The subordinate's hand is the only control over how long the access takes.
A fast clerk's hand is always up. A subordinate that is always ready ties PREADY high — assign pready = 1'b1;. Every access then completes in its first access cycle. Readiness is the default; backpressure is the exception.
The stamp is the finish, and only then does anything commit. A write is captured and PRDATA is valid on the single cycle PENABLE and PREADY are both high. While the hand is down, the form sits uncommitted on the counter.

4. Real SoC / hardware context

In hardware, PREADY is the subordinate's output that the manager's transfer FSM samples each access cycle to decide whether to finish or wait. A fast subordinate ties it high and the access always completes in one cycle. A subordinate that needs time generates PREADY from a small piece of state — a counter or a state bit — that holds it low for a few cycles after being accessed, then raises it.

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Snippet

// PREADY generation in a subordinate that needs a few cycles (teaching sketch
// — not a full slave). It holds PREADY low for WAIT_CYCLES after being
// selected in ACCESS, then asserts PREADY high for the single completion.
// A FAST subordinate would skip all of this and just: assign pready = 1'b1;
localparam int WAIT_CYCLES = 3;
logic [1:0] wait_cnt;
logic       pready;
 
always_ff @(posedge pclk or negedge presetn) begin
  if (!presetn) begin
    wait_cnt <= '0;
    pready   <= 1'b0;
  end else if (psel && penable && !pready) begin
    // In ACCESS, still counting down the wait state: hold PREADY low.
    if (wait_cnt == WAIT_CYCLES - 1) pready <= 1'b1;  // ready next cycle
    else                            wait_cnt <= wait_cnt + 1'b1;
  end else begin
    // Transfer completed (PREADY was high) or bus idle: reset for next access.
    wait_cnt <= '0;
    pready   <= 1'b0;
  end
end

Two facts fall out of this. First, PREADY is purely an output of the subordinate — the manager reads it but never drives it, so there is exactly one driver and no contention. Second, the manager needs no knowledge of how the subordinate decides: it just samples PREADY during the access phase, holds PSEL, PENABLE, the address and write data stable while PREADY is low, and moves on the cycle PREADY is high. The subordinate's timing is fully encapsulated behind one bit.

Figure 1 — PREADY completing a transfer in two cases against PCLK, with PENABLE high throughout the access phase in both. Top (fast subordinate): in the access cycle the subordinate drives PREADY high at once, so the transfer completes immediately — the dashed marker is the completion edge where PENABLE and PREADY are both high. Bottom (one wait state): the subordinate holds PREADY low for the first access cycle, stretching the phase while PENABLE stays high and the access is held, then asserts PREADY high on the next cycle, where completion lands. PREADY high is the only thing that completes the transfer; PREADY low stretches the access phase.

5. Engineering tradeoff table

PREADY is a deliberately minimal handshake. Each property trades a capability APB does not need for the simplicity and universality it does.

`PREADY` property	What it gives up	What it buys	Why it is correct for APB
Subordinate-driven only	Manager control of duration	One driver, no contention	Only the subordinate knows when it is ready
Low inserts a wait state	Fixed, known latency	Subordinates of any speed on one bus	Slow registers and bridges must be able to stall
Sampled during the access phase	A separate completion bus	Completion folded into the existing handshake	One sample point, no extra wires
One bit, no busy/done split	Rich status reporting	Trivial generation (tie-high, or one counter)	The control plane only needs "ready or not"
High is the single completion cycle	Multi-cycle "settling" reporting	One unambiguous commit edge	Removes all sample-timing guesswork in RTL

The throughline: PREADY spends certainty about latency to buy universality — any-speed subordinates on one bus — and certainty about completion — exactly one cycle commits. For a sparse, latency-insensitive control plane, those are precisely the two properties worth buying.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"The manager drives PREADY." No. PREADY is driven by the subordinate; the manager only samples it during the access phase. Reversing the direction is a fundamental misread of the handshake.
"PREADY low means an error." No. PREADY low is a normal wait state — backpressure. It means "not done yet, keep waiting." Errors are reported separately by PSLVERR, not by PREADY.
"A wait state means the transfer restarts." No. While PREADY is low the access is held, not restarted: PENABLE stays high and the address and data stay stable. Only PREADY going high completes it.
"A fast register still needs wait-state logic." No. A subordinate that is always ready simply ties PREADY high (assign pready = 1'b1;). The access then completes in its first access cycle, every time.
"PREADY is sampled in the setup cycle." No. PREADY matters during the access phase (PENABLE high). In setup nothing is completing, so the manager is not yet looking for completion.
"PREADY can be left floating or X when the subordinate is not selected." Be careful: the manager only samples PREADY during its access phase, but a subordinate that drives a shared/muxed ready must present a defined value; an undriven PREADY reaching the manager can stall or falsely complete a transfer.

7. Interview framing

PREADY is a favourite because a precise answer proves you understand the elastic access phase at the signal level, and a vague one ("it says the slave is ready") proves you do not. Interviewers ask "who drives PREADY?" or "what happens when PREADY is low?"

The strong answer states the contract, not just the role: PREADY is driven by the subordinate and sampled by the manager during the access phase; high completes the transfer on that cycle (write captured, read data valid), low inserts a wait state that holds the access while the manager keeps everything stable. Then deliver the two depth points: PREADY is the subordinate's only lever over timing — there is no other backpressure mechanism — and a fast subordinate ties it high, so readiness is the default and waiting is the exception. Close with the history: APB2 had no PREADY and used fixed two-cycle accesses, so a subordinate could not stall; PREADY was added in APB3 precisely to make the access phase elastic. That arc — from fixed latency to a one-bit ready handshake — is exactly what separates an engineer who understands why APB looks the way it does from one who has only memorised the waveform.

8. Q&A

Figure 2 — a multi-cycle wait state driven by PREADY. After one SETUP cycle, the transfer enters the access phase with PENABLE high. The subordinate holds PREADY low for three consecutive access cycles — its backpressure — while the manager keeps PSEL, PENABLE, the address and the write data stable and nothing commits. In the final cycle the subordinate raises PREADY high, which is the single completion cycle where a write is captured and read data is valid. The bracket marks the held access; the dashed line marks the one completion edge where PENABLE and PREADY are both high.

9. Practice

State the direction. From memory, say who drives PREADY, who samples it, and in which phase it is sampled — then explain why a manager must never drive it.
Write the fast case. Write the one-line RTL a fast, always-ready subordinate uses for PREADY, and state how many cycles each access then takes.
Trace the wait. For a transfer where the subordinate holds PREADY low for two cycles, list PENABLE, PREADY, and whether anything has committed on each access cycle, and identify the single completion cycle.
Find the bug. A subordinate drives PREADY low to signal a failed access. Explain which signal it should have used instead and why PREADY low does not mean "error."
Defend the addition. In two sentences, explain what APB2's fixed two-cycle access forbade and why adding PREADY in APB3 was the right fix for a bus hosting both a fast register and a clock-crossing bridge.

10. Key takeaways

PREADY is the subordinate-driven ready handshake: high completes the transfer on that cycle, low inserts a wait state that stretches the access phase.
It is the subordinate's only lever over transfer timing. There is no other backpressure mechanism in APB — the subordinate raises PREADY to finish and lowers it to wait, and that is the entire model.
It is sampled by the manager during the access phase (PENABLE high), and the manager holds PSEL, PENABLE, address and data stable while PREADY is low.
A fast subordinate ties PREADY high — assign pready = 1'b1; — so the access completes in one cycle. Readiness is the default; waiting is the exception.
PREADY makes the access phase elastic, letting subordinates of any speed share one bus while the manager still gets exactly one unambiguous completion edge.
PREADY was added in APB3. APB2 had fixed two-cycle accesses with no way to stall; PREADY converted that fixed-latency bus into an elastic one — and PREADY low is a wait, never an error (that is PSLVERR).