PSTRB — The Write Strobes

Module 2 told you APB4 added a signal called PSTRB for byte-level writes. That named the feature; it did not give you the contract. To drive PSTRB from a manager or honour it in a subordinate, you need its exact shape: how wide it is, which transfers it applies to, and the per-byte write-enable it maps onto in hardware. PSTRB is the APB4 write byte-strobe bus — one strobe bit per byte lane of PWDATA, where a set bit means "update this byte" and a clear bit means "leave it alone." The single idea to carry: PSTRB turns a write from an all-or-nothing full-word store into a per-byte masked store, which is exactly what lets a write touch part of a word without first reading it back.

1. What problem is being solved?

The problem is writing only some bytes of a word without disturbing the rest, and without a read-modify-write.

Real registers pack independent fields into one addressable word — a control byte here, a threshold byte there. Software often wants to change one field and leave its neighbours untouched. The original APB had no way to express this: a write drove all of PWDATA, and the subordinate took the whole word. To change one byte you had to read the word, patch the byte in software, and write the whole word back — two bus transfers plus a non-atomic gap where another agent could change the other bytes underneath you.

PSTRB removes that whole dance. It carries, alongside PWDATA, a small mask:

• A PSTRB bit that is 1 means "this byte lane of PWDATA is live — update it."
• A PSTRB bit that is 0 means "ignore this byte lane — leave that register byte exactly as it was."

With that mask, a single write transfer can update one byte, two bytes, or all four, and the subordinate applies it directly with per-byte write enables. The read-modify-write disappears, and so does its atomicity hole.

2. Why the lifecycle view is not enough

Module 2 named PSTRB as the APB4 add — "write byte strobes, presented from SETUP like the other access-defining signals." That is the right placement, but placement is not a contract. To wire PSTRB into real RTL you need the exact rules, and the version view leaves three things unstated:

• The exact width and mapping: one strobe bit per byte lane. PSTRB is DATA_WIDTH/8 bits wide — for a 32-bit bus, four bits. PSTRB[i] governs PWDATA[8*i +: 8], byte lane i, and nothing else. It is a one-to-one byte mask, not a count or an encoded field.
• It is write-only — meaningless for reads. PSTRB qualifies write data only. On a read the manager drives it to a don't-care value and the subordinate must ignore it: a read always returns a full word on PRDATA, and the manager keeps only the bytes it wants. There is no "read strobe."
• Backward-compatibility is structural. Drive every PSTRB bit high and the write updates all bytes — exactly APB3 full-word behaviour. So an APB4 manager that always asserts all strobes is indistinguishable from APB3, which is why PSTRB is purely additive.

Knowing the role tells you PSTRB exists for partial writes; knowing the contract tells you which bits drive which bytes on which transfers — which is what you actually need to build or check one.

3. The signal's mental model

The model: PSTRB is a row of per-byte write enables that ride along with the write data.

Think of a register word as four mailboxes side by side, one per byte. PWDATA is the stack of letters you are holding, one for each box. PSTRB is the set of little flags on the boxes: a raised flag (bit 1) says "drop your letter in this box," a lowered flag (bit 0) says "skip this box, whatever is inside stays." You walk the row once; only the flagged boxes get their contents replaced. That is precisely a per-byte write enable — PSTRB[i] is the enable on byte lane i.

Three refinements make the model precise:

• One flag per box, exactly. PSTRB is one bit per byte lane — four bits for a 32-bit word. It is never a single "write part of this" bit and never an address of which byte; it is a parallel mask the full width of the lanes.
• A lowered flag preserves, it does not zero. A PSTRB bit of 0 leaves that register byte at its old value. It does not clear it. The unstrobed lanes of PWDATA are simply ignored — their contents are don't-care.
• The flags only exist for writes. On a read there are no letters to drop, so the flags mean nothing. The manager may leave them at anything; the subordinate honours them only on a write and returns a whole word on a read.

4. Real SoC / hardware context

In hardware, PSTRB is the cleanest possible expression of a per-byte write enable. The subordinate decodes the address once, and at the completion edge it updates each byte lane of the target register only if that lane's strobe is set. There is no read step, no merge in software — the byte mask is applied directly in the register-write logic.

// Per-byte strobed write inside an APB4 subordinate (teaching sketch).
// A 32-bit register: each byte lane updates only if its PSTRB bit is set,
// and only at the transfer's completion edge.
logic [31:0] reg_q;
 
// write_commit is the subordinate's completion condition for a write:
//   PSEL & PENABLE & PWRITE & PREADY, all high on this edge.
wire write_commit = psel & penable & pwrite & pready;
 
always_ff @(posedge pclk or negedge presetn) begin
  if (!presetn)
    reg_q <= 32'h0;
  else begin
    for (int i = 0; i < 4; i++)
      if (write_commit && pstrb[i])           // per-byte write enable
        reg_q[8*i +: 8] <= pwdata[8*i +: 8];  // strobed lanes only; others hold
  end
end

Two facts fall straight out of that loop. First, a byte lane whose PSTRB bit is 0 is simply not assigned, so it holds its previous value — preservation is the natural behaviour of a clocked register, not extra logic. Second, the same block handles a full-word write for free: when every PSTRB bit is 1, all four lanes update, which is exactly APB3 behaviour, so the subordinate needs no separate "full word" path.

On the manager side, PSTRB is presented from SETUP alongside PADDR and PWDATA and held stable through ACCESS, like every access-defining signal. A bridge that translates a sub-word AXI write strobe down to APB simply maps the relevant byte enables onto PSTRB. On a read the manager drives PSTRB to a don't-care — it is not part of the read contract — and the subordinate ignores it.

5. Engineering tradeoff table

PSTRB is a deliberately small, optional signal. Each property trades a capability APB does not need for the partial-write power it does.

The throughline: PSTRB does exactly one job — mask which bytes of a write land — and maps onto the cheapest possible hardware, a per-byte write enable. Everything else about a write (address, direction, completion) is unchanged, so PSTRB adds power without adding a new mechanism to the transfer.

6. Common RTL / waveform mistakes

7. Interview framing

PSTRB is a favourite because a precise answer proves you understand byte lanes and write enables, and a vague one ("it does byte writes") proves you have not built one. Interviewers ask "what is PSTRB?" or "how do you write one byte of a register over APB?"

The strong answer states the contract, not just the feature: PSTRB is the APB4 write byte-strobe bus, one bit per byte lane of PWDATA, where a set bit updates that byte and a clear bit leaves it; it is write-only — reads always return a full word and ignore it. Then deliver the two depth points. First, the hardware is a per-byte write enable: if (write_commit && pstrb[i]) reg[8*i +: 8] <= pwdata[8*i +: 8], with unstrobed lanes simply not assigned, so they hold. Second, it replaces a read-modify-write — and crucially makes the partial write atomic, because the subordinate touches only the strobed bytes in a single transfer with no stale read-back to clobber a neighbour. Closing with "all strobes high reproduces APB3 exactly" shows you understand it is a backward-compatible superset, not a new mode.

8. Q&A

9. Practice

1. Map the strobe. For a 32-bit bus, state which PWDATA bits each of PSTRB[3:0] governs, and write the PSTRB value that updates only the top two bytes.
2. Write the enable. From memory, write the per-byte strobed-write RTL for a 32-bit register and explain why unstrobed lanes keep their old value with no extra code.
3. Kill the read-modify-write. A teammate changes one byte of a packed register with a read, a software OR, and a write-back. Rewrite it as a single APB4 strobed write and explain what atomicity bug you removed.
4. Spot the read bug. A subordinate masks PRDATA with PSTRB on reads. State which rule is broken and what a read should return instead.
5. Reduce to APB3. Give the PSTRB value that makes every write behave like an APB3 full-word write, and explain why an APB4 subordinate then needs no separate full-word path.

10. Key takeaways

• PSTRB is the APB4 write byte-strobe bus — one strobe bit per byte lane of PWDATA. A set bit updates that byte; a clear bit leaves it. It is DATA_WIDTH/8 bits wide.
• It is write-only. PSTRB qualifies write data only; a read always returns a full word on PRDATA and the subordinate ignores PSTRB entirely.
• A 0 strobe preserves, it does not zero. The unstrobed lanes of PWDATA are don't-care and the matching register bytes hold their old value.
• The hardware is a per-byte write enable: if (write_commit && pstrb[i]) reg[8*i +: 8] <= pwdata[8*i +: 8], applied at the write completion edge, with unstrobed lanes simply not assigned.
• It replaces a read-modify-write — and makes the partial write atomic. One strobed transfer touches only the chosen bytes, so there is no stale read-back to clobber a neighbour.
• It is a backward-compatible superset. Drive all PSTRB bits high and every write is full-word — identical to APB3 — so the feature is optional and the same RTL covers both, including protection-attributed accesses unchanged.