AMBA APB · Module 3

PCLK — The Bus Clock

PCLK, the single synchronous clock every APB signal is sampled against — who owns it, how its frequency relates to the system clock, and the clock-domain crossing the bridge handles.

Every other APB signal you will study — PSEL, PENABLE, PADDR, PREADY — only has meaning relative to one reference: the cycle. And the cycle is defined by PCLK. PCLK is the single synchronous clock that every APB signal is launched after and sampled on, the rising-edge beat that the entire two-phase protocol counts against. The one idea to carry: APB is a fully synchronous, single-clock bus, and PCLK is that clock — drive a signal after one rising edge, sample it on the next, and the whole protocol reduces to a clean cycle-by-cycle dance with no asynchronous timing to reason about.

1. What problem is being solved?

The problem is giving the whole bus one shared notion of "now."

APB's two-phase model — setup then access — is built entirely on the idea of a cycle. "PENABLE is low for the first cycle," "PREADY is sampled this cycle," "the access completes on this edge" all presuppose that the manager and every subordinate agree, exactly, on where one cycle ends and the next begins. Without a shared clock there is no such agreement, and none of the phase rules can be stated.

PCLK provides that agreement. It is the single clock that:

Defines the cycle boundary every phase rule is written against — a transfer is N cycles of PCLK, no more, no less.
Times every launch. A signal changes value just after a PCLK rising edge and is held stable for the cycle.
Times every sample. The manager and subordinate both capture the bus on the PCLK rising edge, so they read the same value at the same instant.

One clock, one definition of "now," shared by everyone on the bus — that is the foundation the rest of APB is built on, and PCLK is it.

2. Why the lifecycle view is not enough

The transfer lifecycle named PCLK's role in passing: it is "the clock the transfer is counted against." That is the right role, but a role is not a contract. To wire a real APB bridge or peripheral you need the clock's exact properties, and the lifecycle view leaves three things unstated:

There is exactly one clock for the whole bus, and everything is rising-edge. APB is fully synchronous: every signal is registered to PCLK and sampled on its rising edge. There is no second clock, no falling-edge sampling, no asynchronous strobe. The lifecycle says "per cycle"; the contract says one clock, rising edge, for the manager and every subordinate alike.
PCLK is driven on the manager side, by the bridge. It is not a free-standing oscillator the peripherals happen to share; it is sourced and distributed from the manager/bridge that owns the APB segment. A subordinate consumes PCLK, never drives it.
PCLK's frequency is usually not the system frequency. It is commonly divided down from the fast backbone clock so the slow peripheral world runs slower and timing-relaxed. The lifecycle treats the clock as given; the contract tells you it is a deliberately chosen, often-divided clock — and that the bridge spans the boundary between the fast domain and this slow one.

Knowing the role tells you PCLK "times the transfer"; knowing the contract tells you it is a single, manager-driven, rising-edge, usually-divided clock that defines a clock domain — which is what you actually need to integrate APB into an SoC.

3. The signal's mental model

The model: PCLK is the metronome the whole APB segment marches to — one beat, set by the conductor, that everyone counts.

In an orchestra the conductor sets a single tempo, and every player counts the same beats. No player keeps private time; no player plays between beats and expects to be heard. PCLK is that single tempo for the APB bus: the bridge is the conductor, the peripherals are the players, and every phase rule is "on beat N, do X."

Three refinements make the model precise:

One conductor, one tempo. There is a single PCLK for the segment, driven from the manager/bridge side. Every subordinate counts the same beats; none sets its own.
You act on the beat, not between beats. Signals are launched just after a rising edge and sampled on the next rising edge. The space between edges is settling time — the bus is not "read" there. This rising-edge discipline is what makes APB trivially synchronous.
A slower tempo is a feature, not a limitation. PCLK is often a divided version of the fast system clock, so the APB world deliberately marches slower. Sparse control traffic — the odd register read or write — does not need a fast beat, and a slow one relaxes timing and saves power. The fast↔slow boundary is exactly where the bridge sits.

4. Real SoC / hardware context

In a real SoC, the fast interconnect — AXI or AHB on the backbone — runs at the high system frequency. The peripherals behind APB do not. Between them sits the APB bridge, and the bridge is where PCLK is born: it takes the fast clock on its high-speed side and produces PCLK on its APB side, very often by dividing the fast clock down (a ÷2, ÷4, or larger ratio is common). The slow peripheral world then runs entirely on PCLK.

This split is deliberate. A UART, a GPIO block, a timer's configuration registers — these are touched rarely and have no throughput requirement, so clocking them as fast as the CPU backbone would only burn power and tighten timing closure for no benefit. Running them on a slower divided PCLK keeps their logic timing-relaxed and cheap, which is the whole low-speed-peripheral philosophy made concrete in the clock tree.

Because the fast side and the APB side are two different clock domains, the bridge also owns the clock-domain crossing: a request that arrives on the fast clock has to be handed safely into the PCLK domain, and the response handed back. The mechanics of that crossing — synchronizers, handshakes — are the bridge's internal concern and are out of scope here; what matters for understanding PCLK is simply that the boundary exists, that the bridge spans it, and that from the perspective of an APB subordinate the world is gloriously simple: one clock, PCLK, and everything synchronous to it.

Figure 1 — PCLK as the single bus clock. The top row is PCLK; below it, PSEL, PENABLE and PREADY each change just after a rising edge, hold stable across the cycle, and are sampled on the next rising edge (marked by dashed lines). The diagram shows that every APB signal — from manager and subordinate alike — is launched and captured against the same PCLK rising edge. There is one clock for the whole bus, and all APB timing is referenced to it.

Figure 2 — PCLK relative to the fast system clock. The fast backbone (AHB/AXI) runs at the high system frequency; the bridge sits at the boundary and typically generates PCLK by dividing that clock down, so the slow peripheral world runs slower with relaxed timing. The bridge owns the clock-domain crossing between the fast bus and the PCLK domain, so a slow PCLK never constrains the backbone — the cost-to-traffic match a sparse control plane wants. From a subordinate's view there is just one clock, PCLK, and everything synchronous to it.

5. Engineering tradeoff table

PCLK is shaped by APB's goal of a dead-simple, low-cost peripheral bus. Each property trades performance APB does not need for the simplicity and efficiency it does.

`PCLK` property	What it gives up	What it buys	Why it is correct for APB
Single clock for the whole segment	Per-peripheral clocking flexibility	One shared "now"; every phase rule is cycle-exact	Simple synchronous reasoning for the whole bus
Rising-edge sampling only	Half-cycle timing tricks	Trivial, predictable launch/sample discipline	No asynchronous timing to verify in the protocol
Often divided down from the fast clock	Peripheral throughput / low latency	Relaxed timing closure and lower power	Sparse control traffic does not need a fast beat
Driven from the manager / bridge side	Subordinate-side clock control	One source, one clock tree, no contention	The subordinate only ever consumes the clock
Defines a clock domain at the bridge	A single flat clock across the SoC	A clean fast↔slow boundary the bridge owns	Lets the backbone run fast while peripherals stay slow

The throughline: PCLK does one job — be the single synchronous beat for the APB segment — and is deliberately allowed to be slow. Everything that would need a fast clock lives on the other side of the bridge; the APB world trades speed it never uses for timing and power it values.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"PCLK must run at the system clock frequency." No. PCLK is usually divided down from the fast backbone clock so the peripheral world runs slower. Equal frequency is allowed but rarely the design intent — the point of APB is the relaxed slow domain.
"Each APB peripheral can have its own clock." No. There is one PCLK for the segment, sourced from the manager/bridge side; every subordinate samples the same clock. Per-peripheral clocks would break the shared cycle definition the protocol depends on.
"APB signals can be sampled on the falling edge." No. APB is rising-edge synchronous. Signals are launched after a rising edge and sampled on the next rising edge by both ends. Falling-edge sampling is not part of the protocol.
"The subordinate drives or gates PCLK." No. The subordinate consumes PCLK; its only lever on timing is PREADY, not the clock. Driving the clock is the manager/bridge's job.
"The bridge just passes the fast clock straight through as PCLK." Usually not. The bridge typically divides the fast clock and handles the clock-domain crossing between the fast side and the PCLK side; it is a boundary, not a wire.
"A signal must be stable for only the instant of the edge." No. Signals are held stable for the whole cycle and read on the edge; treating the bus as valid only momentarily invites setup/hold mistakes. Drive after the edge, hold across the cycle, sample on the next edge.

7. Interview framing

PCLK looks too basic to ask about, which is exactly why a sloppy answer stands out. Interviewers ask "what clocks an APB bus?" or "how does PCLK relate to the system clock?" to check whether you understand APB as a clock domain, not just a set of signals.

The strong answer states the contract, not just "it is the clock": PCLK is the single synchronous clock for the whole APB segment, driven from the manager/bridge side, and every APB signal is launched after and sampled on its rising edge — there is no second clock and no falling-edge sampling. Then deliver the two depth points: PCLK is usually divided down from the fast system clock, so the peripheral world runs slower and timing-relaxed (correct for sparse control traffic), and the bridge owns the clock-domain boundary between the fast backbone and the slow PCLK domain, handling the crossing so the APB subordinate sees one clean synchronous clock. Showing you know APB is a deliberately slow, single-clock domain at the end of a bridge is what separates an integration-aware engineer from someone who has only seen the waveform.

8. Q&A

9. Practice

State the rule. From memory, write the one-sentence contract for PCLK: how many clocks an APB segment has, which edge signals are sampled on, and who drives it.
Trace a sample. For a transfer drawn against PCLK, mark the edge on which the manager samples PREADY and the edge on which the subordinate samples PADDR, and confirm they are the same kind of edge.
Pick a divide ratio. A backbone runs at 400 MHz and the peripherals only need a 100 MHz PCLK. State the divide ratio the bridge applies and one reason a slower PCLK is preferable here.
Find the bug. A design clocks two APB peripherals on two slightly different clocks and wonders why transfers occasionally misbehave. State which PCLK rule is broken and why one shared clock is required.
Locate the boundary. In an SoC with an AXI backbone and APB peripherals, name the block that owns the clock-domain crossing and describe, at concept level, what it does so the subordinate sees only one clock.

10. Key takeaways

PCLK is the single synchronous clock of the whole APB segment — every signal is timed and sampled against it, and every phase rule is written in PCLK cycles.
APB is rising-edge synchronous: signals are launched after a rising edge, held across the cycle, and sampled on the next rising edge by both ends. No second clock, no falling-edge sampling.
PCLK is driven from the manager / bridge side. Subordinates consume it; their only timing lever is PREADY, never the clock.
PCLK is usually divided down from the fast system clock, so the peripheral world runs slower and timing-relaxed — exactly right for sparse, latency-insensitive control traffic.
The bridge owns the clock-domain boundary. It generates PCLK from the fast clock and handles the fast↔slow crossing, so an APB subordinate sees one clean synchronous clock.
The classic mistakes are domain mistakes: assuming PCLK equals the system clock, giving peripherals separate clocks, sampling on the wrong edge, or treating the bridge as a wire rather than a clock boundary.