AMBA AHB · Module 21

AHB Waveform Checklist

A review checklist for what to verify on every AHB waveform you read. Seven things to check: (1) pipeline alignment (pair each address phase with its data phase one cycle later; data lines up with the previous-cycle address, not the live one); (2) HREADY behavior (low only for real wait states, always eventually high — no hang, address held while low); (3) HTRANS legality (IDLE/BUSY/NONSEQ/SEQ in valid order; SEQ/BUSY only within a burst); (4) HRESP / two-cycle ERROR (OKAY on normal, ERROR as HREADY low then high); (5) data validity (read HRDATA only when HREADY is high, never mid-wait); (6) burst pattern (SEQ-beat addresses follow the type and length); (7) HSEL one-hot + the addressed slave matches. The #1 habit: anchor on the pipeline and HREADY first, because most misreads pair data with the wrong address or read data during a wait state.

The fourth checklist is the AHB Waveform Checklist: what to verify on every AHB waveform you read — in a debug session, a review, a sim trace. It's the waveform-reading skill turned into a repeatable check you run every time, so you never misread. There are seven things to check: (1) pipeline alignment — pair each address phase with its data phase one cycle later; data lines up with the previous-cycle address, not the live one; (2) HREADY behavior — low only for real wait states, always eventually high (no hang), address held while low; (3) HTRANS legality — IDLE/BUSY/NONSEQ/SEQ in valid order; SEQ/BUSY only within a burst; (4) HRESP / two-cycle ERROR — OKAY on normal, ERROR as HREADY low then high; (5) data validity — read HRDATA only when HREADY is high, never mid-wait; (6) burst pattern — the SEQ-beat addresses follow the type and length; (7) HSEL one-hot + the addressed slave matches. The single most important habit is to anchor on the pipeline and HREADY first, because most misreads come from pairing data with the wrong address or reading data during a wait state. This chapter walks each check with what to look for.

1. What Is It?

This checklist is what to verify on every AHB waveform — run it every time you read one. The seven checks:

(1) Pipeline alignment (first) — pair each address phase with its data phase (+1 cycle); data ↔ the previous-cycle address (not the live one).
(2) HREADY + (3) HTRANS — HREADY low only for real waits, always eventually high, address held while low; HTRANS legal (SEQ/BUSY only in a burst).
(4) HRESP + (5) data validity — OKAY/two-cycle ERROR; read HRDATA only when HREADY is high (never mid-wait).
(6) burst pattern + (7) HSEL — SEQ-beat addresses follow the type/length; HSEL one-hot, addressed slave matches.

Figure 1 — the AHB waveform review checklist, seven things to check on every waveform. 1. Pipeline alignment (first): pair each address phase with its data phase one cycle later, and confirm read/write data lines up with the address from the previous cycle, not the live one. 2. HREADY behavior: low only for legitimate wait states, always eventually high (no hang), and the master holds the address stable while it's low. 3. HTRANS legality: a legal IDLE/BUSY/NONSEQ/SEQ order, with SEQ and BUSY only within a burst. 4. HRESP and the two-cycle ERROR: OKAY on normal transfers, any ERROR as the two-cycle pattern (HREADY low then high). 5. Data validity: read HRDATA only when HREADY is high, never mid-wait. 6. Burst pattern: the SEQ-beat addresses follow the declared burst type (incrementing or wrapping) with the right length. 7. HSEL and decode: HSEL is one-hot and the addressed slave matches the address. Anchor on the pipeline and HREADY first, because most waveform misreads come from pairing data with the wrong address or reading data during a wait state.

So the waveform checklist makes waveform reading reliable — a fixed set of checks you run every time, so a misread doesn't slip through. The value is consistency under pressure: in a debug session (stressed, tired, staring at a wall of signals), it's easy to misread — pair data with the wrong address, miscount waits, miss the two-cycle ERROR. The checklist forces the disciplined read every time. And it's ordered: pipeline + HREADY first, because those are where most misreads happen. So this chapter is the waveform-review discipline. So run the checklist on every waveform.

The AHB waveform checklist (every waveform): (1) pipeline alignment (data ↔ previous-cycle address); (2) HREADY (real waits, always eventually high, address held); (3) HTRANS legal (SEQ/BUSY only in a burst); (4) HRESP (two-cycle ERROR); (5) data validity (read HRDATA only when HREADY high); (6) burst pattern (SEQ addresses follow the type); (7) HSEL one-hot. The #1 habit: anchor on the pipeline + HREADY first

The AHB waveform checklist in one frame: what to verify on every AHB waveform — the reading discipline, anchored on the pipeline and HREADY. (1) Pipeline alignment (first): pair each address phase with its data phase one cycle later, and confirm the read/write data lines up with the address from the previous cycle (the captured address), not the live HADDR (which has advanced). Check: data ↔ the address one cycle back. (2) HREADY behavior: HREADY goes low only for legitimate wait states and always eventually goes high (no hang); the master holds the address stable while it's low. Check: waits are real and bounded; the address is held; HREADY recovers. (3) HTRANS legality: the HTRANS sequence is legal — IDLE/BUSY/NONSEQ/SEQ in valid order, with SEQ and BUSY only within a burst (no SEQ straight out of IDLE). Check: the sequence is legal. (4) HRESP / two-cycle ERROR: OKAY on normal transfers; any ERROR is the two-cycle pattern (HRESP=ERROR with HREADY low then high). Check: ERROR is two cycles (distinguish from a wait). (5) Data validity: read HRDATA only when HREADY is high — never take a mid-wait value as the data. Check: the data is read at the HREADY-high cycle. (6) Burst pattern: the SEQ-beat addresses follow the declared burst type (incrementing or wrapping) with the right length. Check: the address sequence matches the type. (7) HSEL + decode: HSEL is one-hot (exactly one slave selected), and the addressed slave matches the address (the read data comes from the selected slave). Check: HSEL is one-hot; the slave matches. The #1 habit: anchor on the pipeline and HREADY first — because most misreads come from pairing data with the wrong address (the pipeline) or reading data during a wait state (HREADY).

2. Why Does It Exist?

This checklist exists because waveform reading is error-prone (especially under debug pressure) — and because two specific misreads dominate (wrong-address pairing and mid-wait reading, both rooted in the pipeline/HREADY) — and because a misread waveform misleads (you chase the wrong bug, or miss a real one).

The waveform reading is error-prone is the root: a waveform is a wall of signals, and you read it under pressure (debugging, tired). It's easy to misread — misalign a phase, miscount a wait. So reliable reading needs a discipline, not eyeballing. So this checklist exists to make reading reliable. So reading is error-prone. So use a checklist.

The two misreads dominate is the focus: most AHB waveform errors are two specific mistakes — pairing data with the wrong (live) address (the pipeline) and reading data during a wait state (HREADY). So the checklist front-loads those (anchor on the pipeline + HREADY). So it exists to catch the dominant misreads. So it's the focus. So anchor on those first.

The a misread misleads is the stakes: a misread waveform misleads — you attribute data to the wrong address (chasing a phantom bug) or miss a real one (it looks fine). So a misread is worse than not reading (it gives false information). So the checklist exists to prevent misleading misreads. So it's the stakes. So read it right. So this checklist exists because: waveform reading is error-prone (a wall of signals under pressure — the root); two misreads dominate (wrong-address, mid-wait — both pipeline/HREADY — the focus); and a misread misleads (chasing phantoms / missing real bugs — the stakes). So the AHB waveform checklist is the reading discipline — anchored on the pipeline and HREADY — applied to every waveform. So this chapter is the waveform-review discipline. So run it every time.

3. Mental Model

Model the waveform checklist as a radiologist reading a scan with a systematic search pattern. A radiologist doesn't just glance at an X-ray and call it — they follow a fixed search pattern, checking each region in order, every time, because a glance misses things and the cost of a missed finding is high. They know the two most common errors — satisfaction of search (stopping after the first finding) and missing a subtle but critical detail — so their pattern is designed to force a complete, ordered read that catches those. Reading an AHB waveform is the same: you don't glance and call it; you run a fixed checklist — pipeline alignment, HREADY, HTRANS, HRESP, data validity, burst, HSEL — anchoring first on the two places misreads happen (the pipeline pairing and HREADY), every waveform, because a glance pairs data with the wrong address and the cost of a misread is chasing the wrong bug.

A radiology reading room where a radiologist reads a scan with a systematic search pattern. They don't just glance at an X-ray and call it — they follow a fixed search pattern, checking each region in order, every time, because a glance misses things and the cost of a missed finding is high. They know the two most common errors — satisfaction of search (stopping after the first finding, missing a second) and missing a subtle but critical detail — so their pattern is designed to force a complete, ordered read that catches those. Reading an AHB waveform is the same: you don't glance and call it; you run a fixed checklist — pipeline alignment, HREADY, HTRANS, HRESP, data validity, burst, HSEL — anchoring first on the two places misreads happen (the pipeline pairing and HREADY), every waveform, because a glance pairs data with the wrong address and the cost of a misread is chasing the wrong bug.

This captures the checklist: the radiologist not glancing = not eyeballing the waveform; the fixed search pattern, region by region = the fixed checklist, check by check; every time = on every waveform; the cost of a missed finding = the cost of a misread (chasing the wrong bug); knowing the two common errors and designing the pattern around them = anchoring on the pipeline + HREADY (where misreads dominate); forcing a complete ordered read = running the checklist in order. Don't glance — run the search pattern, region by region (check by check), anchored on where errors happen, every scan (waveform).

Here is a waveform read with the checklist — the pipeline and HREADY anchored first:

Reading with the checklist: pipeline + HREADY anchored (data valid at HREADY-high)

4 cycles

Figure 2 — a waveform read with the checklist. Check 1, pipeline alignment: A0's address phase is cycle 1; its data D0 returns in the data phase — but HREADY is low in cycle 2 (a wait state), so the data isn't valid until HREADY goes high in cycle 3. Check 2, HREADY: low for one wait state (cycle 2), then high — no hang, and the master holds A0 stable. Check 5, data validity: read D0 only at cycle 3 where HREADY is high, NOT the mid-wait cycle 2. So the correct read pairs D0 with A0 (the address from before the completing data phase) and reads it at the HREADY-high cycle. The two anchored checks (pipeline + HREADY) prevent the two dominant misreads.

The model's lesson: don't glance — run the search pattern, check by check, anchored on where errors happen (pipeline + HREADY), every waveform. In the figure, the two anchored checks catch the two dominant misreads: data validity (read D0 at HREADY-high, not the mid-wait value) and pipeline alignment (pair D0 with A0, the captured address). Run those first, every time.

4. Real Hardware Perspective

The substance behind each check is the protocol structure you've learned — so each checklist item maps to a chapter, and the check applies that structure to the picture.

The pipeline, HREADY, HTRANS, HRESP: the checks — (1) pair data ↔ previous address (pipeline); (2) HREADY real/bounded/held; (3) HTRANS legal; (4) the two-cycle ERROR. So the checklist applies the pipeline, HREADY, HTRANS, and HRESP structure (see Pipelined Operation, What HREADY Means, Slave Wait States, HTRANS, Two-Cycle ERROR Response). So they're the core reads. So pair, count, check legality and the response.

Figure 3 — the two most common AHB waveform misreads, with the correct reading for each. Misread 1, pairing data with the wrong address: reading HRDATA against the same-cycle HADDR — but the bus is pipelined, so the data belongs to the address from one cycle earlier (the captured address), not the live HADDR which has advanced; the correct reading pairs the data with the address one cycle back. Misread 2, reading data during a wait state: taking the HRDATA value in a cycle where HREADY is low as the result — but during a wait the data isn't valid yet; the read data is only valid when HREADY is high; the correct reading reads HRDATA only when HREADY is high. The fix for both is the same anchoring habit: find the cycle where HREADY is high (the data is valid there) and pair that data with the address from one cycle before the completion. These two misreads, both rooted in the pipeline and HREADY, are why you anchor on them first.

The data validity, burst, HSEL: the checks — (5) read HRDATA at HREADY-high; (6) burst addresses follow the type; (7) HSEL one-hot. So the checklist applies the data-validity, burst, and decode structure (see HRDATA Muxing, Single vs Burst Transfer, HBURST, HSEL). And the systematic method is the waveform-debug methodology. So in practice, the waveform checklist is the protocol structure applied to the picture — anchored on the pipeline and HREADY. So in practice, know the structure and check it on every waveform. So that's the review.

5. System Architecture Perspective

At the debug/review level, the checklist is a reading discipline — it prevents the dominant misreads (by anchoring on the pipeline and HREADY), makes reading repeatable (the same checks every time), and turns the reading skill into a habit (so it's reliable under pressure).

The prevents the dominant misreads: the two dominant misreads (wrong-address, mid-wait) are prevented by the first two anchored checks. So the checklist targets the highest-frequency errors. So at the debug level, it prevents the common misreads. So anchor on those. So it's targeted.

The reliable under pressure: a checklist (vs eyeballing) makes reading reliable even when you're stressed/tired (debug) — the discipline is external, not dependent on focus. So at the debug level, the checklist makes reading reliable under pressure. So run it even when rushed. So it's robust. So at the debug/review level, the checklist is a reading discipline that prevents the dominant misreads (anchoring on the pipeline + HREADY) and is reliable under pressure (a habit, not a guess). So the waveform checklist is where reading becomes reliable — making anchoring on the pipeline and HREADY the key to never misreading. So run it every waveform, anchored first. So the checklist makes reading reliable.

6. Engineering Tradeoffs

Using the waveform checklist embodies the anchor-first, read-don't-glance, every-time discipline.

Checklist vs glance. A checklist (ordered checks) reliably reads; a glance misreads (especially under pressure). Run the list.
Anchor-first vs read-in-order-of-rows. Anchoring on the pipeline + HREADY (the dominant misreads) first is high-yield; reading rows top-to-bottom misses the pairing. Anchor first.
Data at HREADY-high vs any HRDATA. Read HRDATA only at HREADY-high; a mid-wait value is not the data. Gate on HREADY.
Every time vs only when confused. Run the checklist every waveform — even ones that look obvious. Obvious-looking misreads are the sneakiest.

The throughline: *the AHB waveform checklist is the reading discipline for every waveform — seven checks: (1) pipeline alignment (data ↔ previous address), (2) HREADY (real waits, always eventually high, address held), (3) HTRANS legality, (4) HRESP (two-cycle ERROR), (5) data validity (read at HREADY-high), (6) burst pattern, (7) HSEL one-hot). The #1 habit: anchor on the pipeline and HREADY first (the dominant misreads). At the debug level, it prevents the common misreads and is reliable under pressure.

The two misreads to never make: pairing data with the wrong (live) address — the data belongs to the address one cycle earlier (the pipeline) — and reading HRDATA during a wait state — it's only valid when HREADY is high. Both are fixed by one habit: find the HREADY-high cycle (data valid there) and pair that data with the address one cycle before it. Anchor on the pipeline + HREADY on every waveform

The two dominant misreads the checklist exists to prevent — and the one habit that fixes both: (1) Pairing data with the wrong address. The single most common misread: reading HRDATA (or HWDATA) against the HADDR in the same cycle. But the bus is pipelined — the data belongs to the address one cycle earlier (the captured address); by the data phase, the live HADDR has advanced to the next transfer. So pairing data with the live address attributes it to the wrong address — you report the wrong thing (a read of A5 returning A4's data). Fix: pair data with the address one cycle back. (2) Reading data during a wait state. The second most common: taking the HRDATA value in a cycle where HREADY is low as the result. But during a wait state, the data is not valid yet (the slave may be stale or not driving); read data is only valid in the cycle where HREADY is high. So a mid-wait value is garbage. Fix: read HRDATA only when HREADY is high. The one habit that fixes both: find the cycle where HREADY is high — that's where the data is valid — and pair that data with the address from one cycle before that completion. Both misreads are rooted in the pipeline (the one-cycle offset) and HREADY (validity gating) — which is exactly why you anchor on those two first on every waveform. A few other checks round it out: miscounting wait states (count HREADY-low cycles carefully); confusing a wait with the first ERROR cycle (check HRESP — OKAY = wait, ERROR = the error sequence); and misreading a burst (trace the SEQ addresses against the type). But the two anchored checks (pipeline + HREADY) catch the majority — run them first, every time. (See Pipelined Operation, What HREADY Means, and Two-Cycle ERROR Response.)

7. Industry Example

A concrete walk — reading a sim waveform during a debug session.

An engineer is debugging a failing AHB test and pulls up the simulation waveform.

(1) Pipeline alignment. They first anchor on the pipeline: they line up each address phase with its data phase one cycle later, mentally tagging which data belongs to which address. They confirm the read data they're examining belongs to the address from the previous cycle, not the live HADDR. ✓
(2) HREADY. They check HREADY: it goes low for two cycles (two wait states) on one transfer, then high — no hang. The master held the address stable across the wait. ✓
(5) Data validity. Critically, they read HRDATA only at the cycle HREADY goes high — not the mid-wait values, which they recognize as not-yet-valid. ✓ (This is where a glance would have grabbed garbage.)
(3) HTRANS + (4) HRESP. They check the HTRANS sequence is legal (a NONSEQ then SEQ beats — a burst), and they spot a two-cycle ERROR on the last beat (HREADY low then high with HRESP=ERROR) — not a wait state, an error. ✓
(6) Burst + (7) HSEL. They trace the burst addresses (0x20, 0x24, 0x28, 0x2C — an INCR4), and confirm HSEL is one-hot, selecting the expected slave. ✓
The finding. Anchoring on the pipeline and HREADY, they correctly read the transaction — and found the bug: the failing transfer's read data was being compared against the wrong address by the testbench's monitor (which paired it with the live HADDR). The waveform was correct; the monitor had the pipeline misread. The checklist's pipeline anchor located the issue.

The example shows the checklist in use: a disciplined, anchored read that correctly interpreted the transaction and located a pipeline-misread bug — which a glance would have missed (or mis-attributed). This is how you read an AHB waveform reliably.

8. Common Mistakes

Waveform-checklist misconceptions

"I'll just glance at it." No — run the checklist. A glance pairs data with the wrong address or grabs a mid-wait value.
"The data goes with the same-cycle address." No — it belongs to the address one cycle earlier (the pipeline). Pair with the previous address.
"HRDATA is valid whenever I see it." No — only at HREADY-high. A mid-wait value is not the data.
"That HREADY-low cycle is a wait." Check HRESP — OKAY = a wait; ERROR = the first cycle of the two-cycle error. They look the same but mean different things.
"Read the signal rows top to bottom." No — anchor on the pipeline + HREADY first (where misreads happen), then read the rest in context.
"Obvious-looking waveforms don't need the checklist." No — obvious-looking misreads are the sneakiest. Run it every time.

9. Interview Insight

The waveform checklist shows reading discipline — being able to list what you verify on a waveform (anchored on the pipeline and HREADY) signals you can read AHB timing reliably.

Figure 4 — the AHB waveform checklist in one card: (1) pipeline alignment (data ↔ previous address); (2) HREADY (real waits, always eventually high, address held); (3) HTRANS legal (SEQ/BUSY only in a burst); (4) HRESP (two-cycle ERROR); (5) data valid only at HREADY-high; (6) burst pattern (SEQ addresses follow the type); (7) HSEL one-hot + the addressed slave matches. The #1 habit: anchor on the pipeline and HREADY first, because most misreads pair data with the wrong address or read data during a wait state. Takeaway: the checklist is the reading discipline applied to every waveform, anchored on the pipeline.

If asked what you verify when reading an AHB waveform, recite the checklist: (1) pipeline alignment (pair data with the previous-cycle address), (2) HREADY (real waits, always eventually high, address held), (3) HTRANS legality, (4) HRESP (the two-cycle ERROR), (5) data validity (read HRDATA only at HREADY-high), (6) burst pattern, (7) HSEL one-hot. Stress the #1 habit: anchor on the pipeline and HREADY first, because most misreads are pairing data with the wrong address or reading mid-wait data. That signals you can read AHB timing reliably — that you don't glance and guess, you run a disciplined, anchored read every time — exactly the skill real debug requires.

10. Practice Challenge

Practice the waveform review.

The seven checks. List them (pipeline, HREADY, HTRANS, HRESP, data validity, burst, HSEL) and what to look for in each.
The two misreads. Explain the two dominant misreads (wrong-address, mid-wait) and the one habit that fixes both.
Wait vs ERROR. Explain how to distinguish an HREADY-low wait from the first ERROR cycle (check HRESP).
Data validity. Explain why you read HRDATA only at HREADY-high.
The anchor. Explain why you anchor on the pipeline and HREADY first.

11. Key Takeaways

The AHB waveform checklist is the reading discipline for every waveform — run it every time, don't glance.
Seven checks — (1) pipeline alignment, (2) HREADY, (3) HTRANS legality, (4) HRESP (two-cycle ERROR), (5) data validity, (6) burst pattern, (7) HSEL one-hot.
Anchor on the pipeline and HREADY first — the two dominant misreads (wrong-address pairing, mid-wait reading) live there.
The one habit — find the HREADY-high cycle (data valid there) and pair that data with the address one cycle before it. This fixes both dominant misreads.
Wait vs ERROR — both have HREADY low; check HRESP (OKAY = wait, ERROR = the error sequence).
Run it every time — even obvious-looking waveforms; obvious-looking misreads are the sneakiest. A misread misleads (chases the wrong bug).

12. What Comes Next

You can now read AHB waveforms reliably. The last two checklists are the interview revision lists:

AHB Interview Checklist (next) — the last-mile revision list before an AHB interview.
Common Mistakes Checklist — the recurring AHB mistakes to never make.

To revisit the structure these checks apply, see Pipelined Operation, What HREADY Means, Two-Cycle ERROR Response, Single vs Burst Transfer, and Waveform-Based Debug Methodology.