HSIZE

This chapter covers HSIZE, the transfer-size signal — how many bits move in each beat. It is a small 3-bit signal, but it sits at the centre of two important relationships: with HADDR (through the alignment rule introduced in 3.2) and with the data bus width (which it must never exceed). We will give the full encoding, see how HSIZE and the low address bits together select which byte lanes carry the data, and pin down the two hard rules that govern every legal access. HSIZE is where "how big is this access?" gets its precise answer.

1. What Is It?

HSIZE is a 3-bit address-phase signal, driven by the manager, giving the size of each data beat — how many bits transfer per beat. The encoding doubles each step:

• 000 — 8 bits (byte)
• 001 — 16 bits (halfword)
• 010 — 32 bits (word)
• 011 — 64 bits (doubleword)
• 100 — 128 bits, 101 — 256 bits, 110 — 512 bits, 111 — 1024 bits

On the 32-bit data bus that most AHB systems use, the everyday values are byte, halfword, and word (000, 001, 010); the larger sizes apply only to wider data buses. HSIZE answers one focused question — how wide is each beat — and that answer feeds two relationships: it must not exceed the data bus width, and it dictates the address alignment.

2. Why Does It Exist?

HSIZE exists because a byte-addressable bus must support accesses of different widths — a processor reads bytes, halfwords, and words depending on the data type — and the subordinate must know the width to handle the access correctly.

A memory or peripheral cannot interpret an access correctly without knowing its size. For a write, the subordinate must know which bytes of the data bus are meaningful — a byte write touches one byte lane, a word write touches four. For a read, it must drive the correct width of data. And the width determines which byte lanes are active, which the subordinate needs to route data to or from the right storage. HSIZE carries that width in the address phase, alongside the address and direction, so the subordinate is fully informed before the data phase.

The reason HSIZE is needed (rather than inferable) is that the same address can be accessed at different sizes. The byte at address 4, the halfword at address 4, and the word at address 4 are three different, legal accesses that touch different amounts of data — HADDR alone cannot distinguish them. HSIZE is the signal that says which one this is. Together, HADDR (where) and HSIZE (how wide) fully locate the bytes being accessed.

The encoding goes up to 1024 bits because AHB is meant to scale to wide, high-bandwidth data buses (a memory controller might have a very wide internal bus). The width of HSIZE's encoding allows the protocol to express beats as wide as those buses support, future-proofing it beyond the common 32-bit case. But the encoding is always constrained by the actual data bus: you cannot move more bits in a beat than the bus has wires, which is the first of the two hard rules.

3. Mental Model

Model HSIZE as the package size on the shipping label, where the truck has a fixed number of lanes.

The shipping label says not just where (HADDR) and which direction (HWRITE) but how big the package is (HSIZE) — a small box, a medium one, a full pallet. The truck (the data bus) has a fixed number of lanes (byte lanes), and the package size determines how many lanes it occupies. A full-pallet shipment (a word, on a 32-bit bus) fills all the lanes; a small box (a byte) occupies one lane, and which lane is decided by the precise address. You obviously cannot ship a package bigger than the truck — a 64-bit beat will not fit on a 32-bit bus.

Watch three differently-sized accesses on the bus:

The model's lesson: HSIZE is the package size, the data bus is the truck, and the address must place the package on a natural boundary. A byte fits anywhere, a halfword on even addresses, a word on multiples of four — and nothing may exceed the truck's lane count. HSIZE travels with the address every transfer, fixing the width before the data moves.

4. Real Hardware Perspective

In hardware, HSIZE drives the byte-lane selection logic and is bound by the data bus width, and its relationship with the low address bits is the concrete mechanism.

On a 32-bit data bus there are four byte lanes. The subordinate's logic uses HSIZE to know how many lanes are active and the low address bits to know which: a word (HSIZE=word) uses all four lanes and requires the low two address bits to be zero (alignment); a halfword uses two lanes, selected by address bit 1, requiring the lowest bit to be zero; a byte uses one lane, selected by the low two address bits, with no alignment constraint. This is exactly why alignment exists — it keeps the low address bits in a state that makes byte-lane selection unambiguous. HSIZE and the aligned HADDR together tell the hardware precisely which wires carry meaningful data.

The first hard rule is physical: HSIZE must not exceed the data bus width. You cannot transfer a 64-bit beat on a 32-bit bus — there are not enough wires. So on a 32-bit bus, legal HSIZE values are byte, halfword, and word (000–010); the wider encodings are only valid on correspondingly wider buses. A manager that drove HSIZE wider than the bus would be requesting an impossible transfer, and the system is not built to handle it. This rule ties HSIZE to a system-integration fact (the data bus width) that must be respected.

The second hard rule is the alignment relationship with HADDR from chapter 3.2, now seen from HSIZE's side: the address must be aligned to the size. These two rules — width-bounded and size-aligned — are what make every legal HSIZE/HADDR combination map cleanly onto the byte lanes. A subordinate built to a fixed data bus width relies on managers honouring both; violating either produces undefined behaviour, since the byte-lane mapping would be ambiguous or impossible.

5. System Architecture Perspective

At the system level, HSIZE connects the bus to the data bus width of the subsystem and to how software and masters generate accesses.

The data bus width is a fundamental architectural parameter of an AHB subsystem, and HSIZE's legal range is bounded by it. A 32-bit subsystem supports up to word beats; a 64-bit subsystem supports up to doubleword; a wide memory-controller bus might support much wider. So choosing the data bus width is simultaneously choosing the maximum HSIZE — a system decision balancing bandwidth (wider = more bits per beat) against cost (wider = more wires, larger logic). HSIZE is the signal through which that width choice shows up on every transfer.

HSIZE also reflects how masters and software access memory. A processor's load/store of a char, a short, and an int produce byte, halfword, and word accesses respectively — the size comes directly from the data type. A DMA engine configured to move 16-bit samples generates halfword accesses. So HSIZE is the bus-level expression of the data granularity the software and masters work in, and getting it right is part of how the system correctly handles different data types. A mismatch — a master issuing the wrong HSIZE for the data it means to move — corrupts data in ways that track the size error.

There is also a performance dimension: for bulk movement, larger HSIZE (wider beats) moves more data per beat, so a DMA on a wide bus uses the widest legal beat to maximize throughput, while a processor accessing a single byte uses a byte beat. The system's choice of data bus width thus caps the per-beat bandwidth, and HSIZE is how each access expresses how much of that width it uses. Bulk operations push toward the maximum HSIZE; fine-grained accesses use smaller sizes. HSIZE is, in effect, the per-access bandwidth knob within the limit the bus width sets.

6. Engineering Tradeoffs

HSIZE itself is simple, but the decisions around it are real.

• Data bus width: bandwidth vs cost. A wider data bus allows larger HSIZE and thus more bits per beat (higher bandwidth), but costs more wires across the whole bus and interconnect and larger byte-lane logic. The system picks a width balancing the bandwidth its traffic needs against area; HSIZE's maximum follows that choice. The trade is per-beat bandwidth versus wiring/area cost.
• Encoding range vs realistic use. HSIZE encodes up to 1024-bit beats, far beyond the common 32-bit bus, to scale to wide buses — at essentially no cost (the encoding is just 3 bits regardless). The "tradeoff" is really future-proofing for free; the constraint is that only sizes up to the actual bus width are legal on any given system.
• Mandatory alignment vs flexibility. Tying HSIZE to alignment keeps byte-lane mapping clean (the hardware win) but forbids misaligned multi-byte accesses (a software constraint). As in 3.2, AHB chooses the hardware simplicity, and software/compilers/DMA must generate aligned accesses of the right size. The trade is clean hardware versus access-pattern flexibility.
• Per-access size vs fixed-width simplicity. Allowing each access its own size (byte, halfword, word) supports the full range of data types a processor uses, at the cost of the byte-lane selection logic that interprets HSIZE and the address. A fixed-width-only bus would be simpler but could not express sub-word accesses. AHB supports variable size because real software needs it, and pays the modest lane-selection logic.

The through-line: HSIZE is cheap to encode but bound by the real data bus width, and it carries the alignment relationship that keeps byte-lane mapping clean. The interesting decisions are at the system level (how wide to make the data bus, which caps HSIZE) and at the discipline level (honour width and alignment), not in the signal itself.

7. Industry Example

Trace HSIZE through a processor and a DMA on a 32-bit AHB.

• A char access (byte). The processor reads a single byte — say a status flag at address 7. It drives HSIZE = 000 (byte) and HADDR = 7. A byte access has no alignment constraint, so address 7 is fine; the subordinate uses the low two address bits to route the single active byte lane. One byte moves.
• A short access (halfword). The processor reads a 16-bit value at address 4. It drives HSIZE = 001 (halfword) and HADDR = 4 — even, so aligned. Two byte lanes are active, selected by address bit 1. If the processor (buggily) used address 5 for a halfword, it would violate alignment.
• An int access (word). The processor reads a 32-bit value at address 8. It drives HSIZE = 010 (word) and HADDR = 8 — a multiple of 4, aligned. All four byte lanes are active. This is the most common access on a 32-bit system.
• A DMA block move (word beats). A DMA copying a buffer uses HSIZE = word beats to maximize throughput on the 32-bit bus — moving 32 bits per beat is the widest legal size, so it is the most efficient. If the buffer's elements were 16-bit samples and the DMA were configured for halfword, it would use HSIZE = halfword instead, moving 16 bits per beat. The DMA's HSIZE must match the data it is moving, or it corrupts.
• The width ceiling. None of these accesses can use HSIZE wider than word, because the data bus is 32 bits — a 64-bit beat is impossible here. On a 64-bit memory-controller bus, a DMA could use doubleword beats for even more throughput. The data bus width sets the ceiling, and HSIZE expresses each access's use of it.

Every access on the bus carries an HSIZE matched to its data width and an aligned address, and the byte-lane logic uses the two to move exactly the right bytes. The DMA's choice of the widest legal HSIZE for bulk movement, and the processor's per-access sizes matching its data types, are HSIZE doing its everyday job.

8. Common Mistakes

9. Interview Insight

HSIZE questions test the two hard rules and the relationship to byte lanes.

The answer that lands gives the encoding and both rules: "HSIZE is 3 bits giving the beat width — byte, halfword, word, and up to 1024-bit on wide buses. Two hard rules: it must not exceed the data bus width, and the address must be aligned to the size. Together with the low address bits, HSIZE selects which byte lanes carry the data." Volunteering both rules, and the byte-lane relationship, shows you understand HSIZE's role in the data path, not just its encoding.

10. Practice Challenge

Reason from the encoding and the two hard rules.

1. Encode the sizes. Give the HSIZE encoding for byte, halfword, and word, and state the legal range on a 32-bit bus.
2. Check legality. For a 32-bit bus, say whether each is legal: a word at address 8, a word at address 6, a halfword at address 3, a doubleword at address 0.
3. Select the lanes. For a halfword access at address 4 on a 32-bit bus, state which byte lanes are active and which address bit selects them.
4. Distinguish from HBURST. In one sentence, explain how a 4-beat word burst uses HSIZE and HBURST.
5. Diagnose corruption. A DMA completes but corrupts data. Explain how a wrong HSIZE causes silent corruption and why no error is raised.

11. Key Takeaways

• HSIZE is a 3-bit beat-size signal: byte (000), halfword (001), word (010), doubleword (011), up to 1024-bit (111). On a 32-bit bus the legal everyday values are byte, halfword, and word.
• HSIZE is beat width, not beat count — the number and pattern of beats is HBURST. Keep the two distinct.
• Two hard rules: HSIZE must not exceed the data bus width, and the address must be aligned to HSIZE. The first is physical (wire count), the second keeps byte-lane mapping clean.
• HSIZE and the low address bits select byte lanes — how many lanes (HSIZE) and which (address) — which is why alignment to size is required.
• A wrong HSIZE silently corrupts — it completes but touches the wrong byte lanes (extra or partial data), with no error. A classic "data subtly wrong, nothing failed" bug.
• The data bus width caps HSIZE and is a key system parameter; bulk movers use the widest legal size for throughput, while fine-grained accesses use smaller sizes.

12. What Comes Next

You now know how wide each beat is. The next signal says how many beats and in what pattern:

• 3.5 — HBURST (coming next) — the burst-type encoding (SINGLE, INCR, WRAP4/8/16, INCR4/8/16) whose beats each carry this chapter's HSIZE.
• 3.6 — HPROT (coming soon) — the protection and attribute hints that accompany the access.

To revisit the alignment relationship HSIZE shares with the address, see HADDR & HWRITE; for how HSIZE's beats stream as a burst, see Single Transfer vs Burst Transfer and HTRANS. For the broader protocol map, see the AMBA family overview.