Peripheral Selection

This closes Module 11 by applying everything — decoding, HSEL, address maps — to the most common real case: selecting a peripheral. Peripherals (UART, timer, GPIO, …) differ from memories: there are many of them, each tiny (a few registers), and they don't need the speed of the main bus. So they're selected hierarchically and usually grouped on a slower peripheral bus. The address is decoded in three stages of decreasing granularity: the top-level decoder uses the upper address bits to assert the peripheral block's HSEL; a sub-decoder (often inside an AHB-to-APB bridge) uses the middle bits to select one peripheral; and the lowest bits select a register within that peripheral. Each decode stage is small (few comparisons) and matches the physical bus hierarchy (main bus → bridge → peripheral bus). This chapter covers hierarchical peripheral selection, the address-field split, and the bridge that isolates the slow, narrow peripheral bus from the fast main bus.

1. What Is It?

Peripheral selection is how a transfer to a peripheral's register is routed — through a hierarchy of decode stages. One address is decoded three times, at decreasing granularity:

• Top decoder → block. The upper address bits select the peripheral block (asserting its HSEL) — distinguishing "a peripheral access" from RAM, flash, etc.
• Sub-decoder → peripheral. Within the block (often an AHB-to-APB bridge), the middle bits select one peripheral (UART vs timer vs GPIO).
• Register offset → register. The lowest bits select a register within that peripheral.

So peripheral selection is the hierarchical application of decoding (chapters 11.1–11.2) to the peripheral case: a coarse decode selects the block, a fine decode selects the peripheral, and the address offset selects the register. Each stage uses a different slice of the same address. This hierarchy keeps every decoder small (the top decoder compares a few coarse regions; each sub-decoder a few peripherals) and matches how peripherals are physically organized — grouped behind a bridge on a separate, slower peripheral bus. So peripheral selection is the multi-stage, coarse-to-fine routing of a transfer to a specific peripheral register.

2. Why Does It Exist?

Hierarchical peripheral selection exists because peripherals have a distinct profile — many, tiny, and slow — that makes a flat decode (every peripheral compared at the top level) wasteful, and makes grouping them behind a bridge on a slower bus the natural architecture. The hierarchy follows that architecture.

The peripheral profile is the root: peripherals differ from main memories in three ways. Many: a system may have dozens of peripherals (UARTs, timers, GPIO, SPI, I2C, ADC, …). Tiny: each needs only a few registers (tens of bytes), not megabytes. Slow: peripherals run at modest rates (a UART register doesn't need gigabytes-per-second) — they don't need the main bus's high bandwidth. So peripherals are a large number of small, slow targets. This profile shapes everything. So hierarchical selection exists because peripherals are many, tiny, and slow — a profile that calls for special handling.

The reason a flat decode is wasteful is decoder size: if the top-level decoder had to select every individual peripheral (dozens of tiny regions), it would be a large decoder (dozens of comparisons) sitting on the critical main-bus address path — big and slow. Hierarchical decode avoids this: the top decoder selects just the block (one coarse region), and a sub-decoder (off the critical main path) handles the many fine peripheral selections. So each decoder is small. So hierarchy exists to keep decoders small by splitting the many fine selections off the main path. So flat decode is avoided for decoder-size reasons.

The reason peripherals are grouped behind a bridge on a slower bus is efficiency and isolation: since peripherals are slow and don't need the main bus's speed/width, putting them directly on the fast main bus would waste the main bus's capability (and load it with many slow slaves). Instead, peripherals are grouped on a separate, slower, narrower bus (classically APB — the Advanced Peripheral Bus), connected to the main bus through a bridge (an AHB-to-APB bridge). The bridge is one slave on the main bus (occupying the peripheral block's region); behind it, the APB bus and its sub-decoder fan out to the many peripherals. This isolates the slow peripheral traffic from the fast main bus (the main bus isn't held up by slow peripherals) and simplifies the peripherals (APB is a simpler, non-pipelined protocol). So peripherals live behind a bridge for efficiency (don't waste/load the main bus) and isolation (slow traffic separated). So the hierarchy — top decode to the bridge, sub-decode within — follows this physical grouping. So hierarchical peripheral selection exists because peripherals are many/tiny/slow, which makes flat decode wasteful and grouping-behind-a-bridge the natural architecture; the decode hierarchy mirrors that architecture (block → peripheral → register), keeping each decoder small and isolating the slow peripheral bus.

3. Mental Model

Model peripheral selection as the postal hierarchy delivering a letter — the national sorting center routes by the first digits of the postcode to the right city (the block), the city's local post office routes by the next digits to the right neighborhood street (the peripheral), and the mail carrier uses the house number to reach the exact door (the register); each level only looks at its part of the address, and the small local offices handle the many fine deliveries so the national center doesn't have to.

A letter's full address (the bus address) is delivered through a hierarchy. The national sorting center (the top decoder) reads only the first digits of the postcode and routes the letter to the right city (the peripheral block) — it doesn't deal with individual streets, just cities. The city's local post office (the sub-decoder in the bridge) reads the next digits and routes to the right neighborhood/street (the specific peripheral). Finally, the mail carrier uses the house number (the lowest bits) to reach the exact door (the register). Each level looks only at its part of the address — coarse to fine. Crucially, the small local offices handle the many fine deliveries (every street, every house), so the national center (on the critical, high-volume path) stays simple — it only sorts by city. And the local delivery happens on local roads (the slower peripheral bus), not the national highway (the fast main bus) — the highway carries bulk between cities, the slow last-mile happens locally. So a hierarchy of sorters, each reading its slice, with the fine work pushed to small local offices on local roads.

This captures peripheral selection: the full address = the bus address; the national center sorting by first digits = the top decoder (upper bits → block); the local post office = the sub-decoder (middle bits → peripheral); the carrier's house number = the register offset (lowest bits); small local offices handling the many deliveries = the sub-decoder keeping the top decoder small; local roads vs the national highway = the slow peripheral bus vs the fast main bus, joined by the bridge. A coarse-to-fine delivery hierarchy that keeps the high-volume center simple.

Watch a peripheral access decode through the stages:

The model's lesson: a coarse-to-fine delivery hierarchy — national center to city, local office to street, carrier to door. In the waveform, the same address slice-by-slice selects the block, then the peripheral, then the register — three stages, each on its own bits.

4. Real Hardware Perspective

In hardware, peripheral selection is realized as a top-level AHB decoder selecting the bridge, an AHB-to-APB bridge that sub-decodes to per-peripheral PSEL lines on the APB bus, and the peripheral using the low address bits to index its registers.

The top-level AHB decode selects the peripheral block: the main-bus decoder treats the entire peripheral region (e.g. 0x4000_0000–0x4000_FFFF) as one slave — the bridge — and asserts the bridge's HSEL for any address in that region. So from the main bus's view, the whole peripheral subsystem is a single AHB slave (the bridge). This keeps the main-bus decoder small (the peripherals are one coarse region, not dozens). So in hardware, the top decode selects the bridge as one AHB slave.

The AHB-to-APB bridge is the key hardware block: it's an AHB slave on the main bus and an APB master on the peripheral bus. It accepts the AHB transfer (in the peripheral region), then sub-decodes the address (the middle bits) to assert one peripheral's PSEL on the APB bus, and runs the APB transfer to that peripheral. APB is a simpler, non-pipelined protocol (a setup phase then an access phase, with PSEL/PENABLE/PREADY) suited to slow peripherals. The bridge also handles the clock/speed crossing (the APB bus often runs slower) and the protocol conversion (AHB pipelined ↔ APB non-pipelined). So in hardware, the bridge is where the sub-decode happens (HADDR middle bits → one PSEL) and where the main bus meets the slow peripheral bus. (The APB protocol itself is covered in the APB track; here the key point is that the bridge sub-decodes to select one peripheral.)

The register indexing completes the path: once a peripheral is selected (its PSEL/HSEL high), it uses the lowest address bits as a register index — selecting which of its registers the access targets (control register, status register, data register, …). So the peripheral's internal logic decodes the low bits to mux the right register. So in hardware, the full path is: top AHB decode → bridge HSEL; bridge sub-decode → peripheral PSEL; peripheral low-bit decode → register. Three decode stages on three address slices, spanning the AHB main bus, the bridge, and the APB peripheral bus. (In simpler systems without a separate APB bus, peripherals may sit directly on AHB with a flat or lightly-hierarchical decode — but the many/tiny/slow profile still favors grouping and sub-decoding.)

5. System Architecture Perspective

At the system level, hierarchical peripheral selection (and the bridge that enables it) is a partitioning decision — it separates the system into a high-performance main domain and a low-performance peripheral domain, which is fundamental to SoC organization.

The performance partitioning is the core system point: an SoC has a spectrum of components — high-bandwidth (CPU, memory, DMA, accelerators) needing the fast main bus, and low-bandwidth (peripherals) that don't. Grouping the peripherals behind a bridge partitions the system into a high-performance domain (the AHB main bus, with memory and high-speed masters) and a low-performance domain (the APB peripheral bus, with the many slow peripherals). This partition lets each domain be optimized for its needs: the main bus is fast, wide, pipelined; the peripheral bus is simple, narrow, low-power. So at the system level, peripheral selection's hierarchy reflects a fundamental performance partitioning of the SoC — the bridge is the boundary between the fast and slow worlds. This is a defining feature of AMBA-based SoCs (AHB/AXI for performance, APB for peripherals).

The decoupling and scalability view: the bridge decouples the two domains. The main bus isn't loaded or slowed by the many peripherals (they're behind the bridge, on their own bus). The peripheral bus can run at its own clock (often slower, for power), crossing into the main bus's clock at the bridge. And adding peripherals scales cleanly: a new peripheral attaches to the APB bus and gets a sub-decode entry — it doesn't touch the main-bus decoder or load the main bus. So the partition makes the system modular and scalable — peripherals are added/removed in their own domain. So at the system level, hierarchical peripheral selection enables clean decoupling and scalable peripheral integration. This is why the peripheral subsystem (bridge + APB + peripherals) is often a reusable, self-contained block in SoC design.

The power and area view rounds it out: the peripheral bus (APB) is simpler (non-pipelined, narrower) and can be clock-gated or run slow when peripherals are idle — saving power. The simpler protocol also means smaller peripheral interfaces (an APB slave is much simpler than an AHB slave) — saving area across the many peripherals. So grouping peripherals on a simple slow bus saves power and area at scale (dozens of simple APB peripherals vs dozens of full AHB slaves). So at the system level, hierarchical peripheral selection — via the bridge to a slower, simpler peripheral bus — is a foundational SoC partitioning that separates the fast and slow domains, decouples them (no main-bus loading, independent clocking, scalable integration), and saves power and area (simple, slow, gateable peripheral bus). It's how SoCs cleanly organize the many small slow peripherals without compromising the high-performance core — the architectural payoff of the decode hierarchy. So peripheral selection is not just "decode to a peripheral"; it's the realization of a key SoC structural partition.

6. Engineering Tradeoffs

Peripheral selection embodies the hierarchical, partitioned-decode design.

• Hierarchical vs flat decode. Hierarchical decode (block → peripheral → register) keeps each decoder small and matches the bus structure, at the cost of decode stages/latency (the bridge adds a hop). Flat decode (every peripheral at the top) is one stage but makes the top decoder large and loads the main bus. Many/tiny peripherals favor hierarchy.
• Bridge to slow bus vs peripherals on the main bus. A bridge to a slow peripheral bus (APB) isolates slow traffic, saves power/area, and decouples clocks, at the cost of the bridge and the extra hop's latency. Peripherals directly on the main bus avoid the bridge but waste/load the fast bus. Most SoCs use a bridge.
• Grouped peripheral domain vs scattered. Grouping peripherals in one block (behind a bridge) is modular and scalable, at the cost of all peripheral traffic funneling through the bridge. Scattering peripherals across the map is flexible but loses the partition benefits. Grouping is the norm.
• Coarse top region vs fine top region. A coarse top-level region (one block for all peripherals) keeps the top decoder tiny but requires sub-decode; a finer top-level (a few peripheral sub-blocks) balances. Large systems use multiple peripheral blocks/bridges.

The throughline: peripheral selection is hierarchical — the top decoder uses upper address bits to select the peripheral block (the bridge's HSEL), a sub-decoder (in the AHB-to-APB bridge) uses middle bits to select one peripheral (its PSEL), and the lowest bits select a register. Each stage is small and uses a different address slice. The hierarchy follows the physical partition: the many/tiny/slow peripherals are grouped behind a bridge on a slower, simpler peripheral bus — isolating slow traffic from the fast main bus, decoupling clocks, and saving power/area. It's the realization of a foundational SoC performance partition.

7. Industry Example

Trace a peripheral access through the hierarchy.

A microcontroller has the peripheral block at 0x4000_0000 behind an AHB-to-APB bridge; the block holds a UART (0x4000_0000), timer (0x4000_1000), and GPIO (0x4000_2000).

• CPU writes the GPIO output register at 0x4000_2004. The main-bus decoder sees the upper bits (0x4000…) fall in the peripheral region → asserts the bridge's HSEL. From the main bus's view, this is an access to the bridge (one slave).
• The bridge sub-decodes. The bridge accepts the AHB transfer and sub-decodes the middle bits (…2…) → asserts the GPIO's PSEL on the APB bus (not the UART's or timer's). It runs an APB write to the GPIO.
• The GPIO selects the register. The GPIO, selected, uses the lowest bits (…004) to index its output register (offset 0x004) and writes the data. So the three stages — block, peripheral, register — route the write to the exact GPIO register.
• A different peripheral. A read of 0x4000_0008 (UART, register 0x008) takes the same path: block HSEL (bridge) → UART PSEL (sub-decode of …0…) → UART register 0x008. Same hierarchy, different middle/low bits.
• Latency. The peripheral access goes through the bridge (an extra hop) and the APB protocol (setup + access phases) — so it's slower than a main-bus (e.g. SRAM) access. That's fine: the peripheral is slow anyway, and isolating it behind the bridge keeps the fast main bus unencumbered.
• Adding a peripheral. To add an SPI controller, attach it to the APB bus and give it a sub-decode entry (e.g. 0x4000_3000) — no change to the main-bus decoder, no extra load on the main bus. Clean, scalable integration.

The example shows the full hierarchy: the main bus selects the bridge (block), the bridge sub-decodes to the peripheral, and the peripheral indexes its register — three stages on three address slices. The bridge isolates the slow peripheral traffic, the access incurs the bridge's latency (acceptably), and new peripherals integrate cleanly in the peripheral domain. This is how SoCs route to their many small peripherals.

8. Common Mistakes

9. Interview Insight

Peripheral selection is an SoC-organization interview topic — the decode hierarchy, the bridge to a slower bus, and the "block is one slave" framing are the signals.

The answer that lands frames it as hierarchical decode following a system partition: "Peripherals are selected hierarchically, because they're many, tiny, and slow. The top-level main-bus decoder uses the upper address bits to select the peripheral block — which, from the main bus's view, is a single slave: the AHB-to-APB bridge. The bridge then sub-decodes the middle address bits to select one peripheral — asserting that peripheral's select on the slower APB peripheral bus. Finally, the peripheral uses the lowest address bits as a register index to pick the specific register. So one address is decoded in three stages, each on a different slice — block, peripheral, register — and each decoder is small. The reason for the hierarchy is a system partition: peripherals don't need the main bus's speed, so they're grouped behind a bridge on a slower, simpler bus, which isolates the slow peripheral traffic from the fast main bus, lets the peripheral bus run at its own clock for power, and makes adding peripherals scale cleanly without touching the main-bus decoder. The key framing is that the main bus sees the whole peripheral block as one slave — the bridge — and the fine peripheral selection happens behind it." The decode hierarchy, the bridge/partition rationale, and the "block is one slave" framing are the senior signals.

10. Practice Challenge

Reason from peripheral selection.

1. The hierarchy. Describe the three decode stages and which address bits each uses.
2. The bridge. Explain why peripherals are grouped behind an AHB-to-APB bridge on a slower bus.
3. Read the waveform. From Figure 2, trace how 0x4000_2004 and 0x4000_0008 select different peripherals via the same hierarchy.
4. One slave. Explain why the main-bus decoder sees the peripheral block as a single slave and the implications (decoder size, latency, modularity).
5. Partition. Explain the fast/slow system partition the hierarchy reflects and its benefits (isolation, power, scalability).

11. Key Takeaways

• Peripheral selection is hierarchical — the top decoder uses upper bits to select the peripheral block (the bridge's HSEL), a sub-decoder uses middle bits to select one peripheral (its PSEL), and the lowest bits select a register. Three stages, three address slices, coarse to fine.
• The block is one main-bus slave — from the main bus's view, the whole peripheral subsystem is a single slave (the AHB-to-APB bridge); the fine peripheral selection happens behind it on the peripheral bus.
• Peripherals are grouped behind a bridge because they're many, tiny, and slow — putting them on a slower, simpler peripheral bus (APB) isolates slow traffic from the fast main bus, lets the peripheral bus run slow/gated for power, and simplifies peripheral interfaces (less area).
• The hierarchy keeps each decoder small — the top decoder has one coarse region for all peripherals; the sub-decoder a few peripherals — versus a huge flat decoder on the critical main-bus path.
• It reflects a fundamental SoC partition — a high-performance domain (main bus + memory) and a low-performance domain (peripheral bus), decoupled by the bridge, enabling independent clocking and clean, scalable peripheral integration.
• Peripheral accesses incur the bridge's latency (the extra hop + APB phases) — slower than main-bus accesses, by design, since peripherals are slow anyway.

12. What Comes Next

This completes Module 11 — Decoder & Slave Selection. You now understand address decoding, HSEL generation, the default slave, the address map, illegal-address behavior, sparse-map decoding, and hierarchical peripheral selection — the full picture of how a transfer is routed to the right slave (or peripheral register). The next module turns to the most widely-deployed AHB variant:

• Module 12 — AHB-Lite (coming next) — the single-master subset that powers most microcontrollers: why it exists, the single-master simplification, removed arbitration, simplified responses, and AHB-Lite slave design.

To revisit the decode foundations this module built on, see Address Decoding, The Address Map, and Master, Slave, Decoder & Arbiter.