The Two-Phase Pipeline

This opens Module 5 — Address and Data Phase, which examines AHB's two-phase timing in full. You met the pipeline as architecture (chapter 2.5, "Pipelined Operation") and as the reason the address phase precedes the data phase (2.3). This module treats it as the timing reference for the whole protocol — the structure you read timing against. This first chapter establishes that structure precisely: every transfer is an address phase followed by a data phase exactly one cycle later, with a register between them, and the phases of consecutive transfers overlap. Every subsequent Module 5 chapter — address leads data, control/data alignment, read and write timing, hazards, waveform reading — is a view of this one structure. Get it crisp here and the module is straightforward.

1. What Is It?

The two-phase pipeline is AHB's defining timing structure: every transfer happens in two stages, one clock apart:

• An address phase — one cycle in which the master drives the access description (HADDR and control).
• A data phase — the next cycle, in which the data moves.

Between them is effectively a register stage: the address-phase information is captured at a clock edge and used in the following cycle's data phase. So a transfer's data phase is always one cycle after its address phase.

Because the two phases use different parts of the bus (address/control vs data), consecutive transfers overlap: while one transfer is in its data phase, the next is in its address phase. After the first transfer fills the pipe, the bus completes one transfer per cycle.

The essence: AHB timing is address now, data next cycle, repeated and overlapped. This is not one feature among many — it is the frame in which every AHB timing statement is made. "The control is valid this cycle, the data next cycle"; "address leads data by one"; "this beat completes when HREADY is high" — all are statements about this two-phase structure. Module 5 is, in effect, a careful tour of this structure from every angle.

2. Why Does It Exist?

The two-phase pipeline exists because AHB needs both time to decode and select a subordinate and high throughput — and a registered, overlapping two-stage structure delivers both at once.

We established the two halves of this in Module 2:

• The address phase must precede the data phase (chapter 2.3) because the subordinate cannot move data until it has been decoded and selected, which takes a cycle. So a transfer is naturally two stages: describe (and decode), then move data.
• The phases overlap to give throughput (chapter 2.5) because the two stages use different parts of the bus, so the next transfer's address phase can run during the current transfer's data phase. This turns "two cycles per transfer" into "one transfer per cycle."

The pipeline exists as the combination of these: a two-stage structure (for decode time) that overlaps (for throughput). One design decision — split each transfer into a registered address stage and a data stage — buys both the decode time and the pipelining. This is why the two-phase pipeline is so central: it is the single structural choice from which AHB's timing behaviour flows.

The reason this module treats it as a timing reference (beyond the architecture view of Module 2) is that reading and reasoning about AHB timing requires holding this structure explicitly. When you look at a waveform, the signals on any given cycle belong to two different transfers — the address phase of one and the data phase of another. Without the two-phase frame, a waveform is confusing; with it, every signal has a clear place ("this is transfer N's address phase, this is transfer N−1's data phase"). So the pipeline exists, for the purposes of this module, as the mental scaffold that makes timing legible. The chapters that follow — the one-cycle lead, control/data alignment, read/write timing, hazards, waveform reading — are all exercises in applying this scaffold.

So the two-phase pipeline exists structurally to give decode time plus throughput, and pedagogically (this module) as the timing reference against which all of AHB's phase behaviour is read and reasoned.

3. Mental Model

Model the pipeline as a two-person assembly: one person reads the next order while the other fulfils the current one.

Person 1 (the address stage) reads each order aloud — "item, quantity, destination" — one order per beat. Person 2 (the data stage) fulfils the order Person 1 read last beat. So at any moment, Person 1 is reading order N while Person 2 is fulfilling order N−1. Both are always busy (the overlap), and a finished order rolls out every beat (one transfer per cycle). The hand-off between them — Person 1 passing the order to Person 2 — is the one-cycle register: the order Person 1 reads this beat is fulfilled by Person 2 next beat.

This captures the three things that matter: the two stages (read vs fulfil), the one-cycle offset (Person 2 is always one order behind), and the overlap (both busy at once). And it explains why a waveform shows two transfers' signals each cycle: at any beat, you see Person 1's current order (the address phase of transfer N) and Person 2's current work (the data phase of transfer N−1).

Watch the pipeline run with phase bands:

The model's lesson: two people, one cycle apart, both always busy — read the next order while fulfilling the current one. The waveform shows it: HADDR climbs A, B, C while HWDATA shows DA, DB, DC one cycle behind. On any cycle, you read both the current address (the order being read) and the current data (the previous order being fulfilled). That dual reading is the two-phase frame.

4. Real Hardware Perspective

In hardware, the pipeline is built from a register stage, and the one-cycle offset is a direct consequence of synchronous design.

The address-phase signals a master drives in cycle N are sampled at the clock edge ending cycle N and used to perform the data movement in cycle N+1. That registering — capture the address/control at the edge, act on it the next cycle — is the pipeline stage. It costs only the registers a synchronous design already has, which is why the pipeline is essentially free (the recurring point from chapter 2.5). The one-cycle offset between address and data is not an arbitrary timing choice; it is the natural result of registering the address phase before the data phase acts on it.

The registering also gives the decode and subordinate setup their cycle (chapter 2.3): during cycle N, while the address is being presented and registered, the decoder resolves the selection and the subordinate prepares — so by cycle N+1 (the data phase) the right subordinate is ready to move data. So the register stage serves double duty: it creates the pipeline offset and provides the decode time. One register, two benefits.

The overlap is a hardware consequence of the address and data buses being separate sets of wires (chapters 2.1, 3.7). Because HADDR/control and HWDATA/HRDATA are distinct, cycle N+1 can carry transfer N's data (on the data bus) and transfer N+1's address (on the address bus) simultaneously — no contention. If the same wires carried both, there would be no overlap; the separate buses are what make the pipeline possible. So the pipeline rests on two hardware facts: a register stage (the offset) and separate address/data buses (the overlap).

A key hardware reading skill, developed across this module: on any cycle, the address bus and data bus belong to different transfers. The address bus shows transfer N's address (its address phase); the data bus shows transfer N−1's data (its data phase). A common waveform-reading error is to read the address and data on the same cycle as belonging to the same transfer — they do not (except in the degenerate first cycle). This dual-transfer-per-cycle nature is the hardware reality the two-phase frame captures, and chapter 5.7 trains reading it.

5. System Architecture Perspective

At the system level, the two-phase pipeline is the timing contract that every master and subordinate is designed against, and it sets the bus's performance ceiling.

Every AHB component is built around the two-phase structure: masters drive address one cycle ahead of data; subordinates decode and prepare in the address phase, then move data in the data phase; the interconnect routes accordingly. So the pipeline is the shared timing contract of the whole system — a master and a subordinate from different vendors interoperate because both honour "address now, data next cycle." This is what makes AHB IP composable at the timing level: the two-phase pipeline is the timing interface everyone implements.

The pipeline also sets the performance ceiling: at best, one transfer per cycle (the full-pipe rate). Real throughput is this ceiling minus the bubbles — IDLE, BUSY, and wait states (chapters 4.6, and Module 6 ahead). So the two-phase pipeline defines peak bus bandwidth (clock rate × bus width, one transfer/cycle), and the system's job is to keep the pipe as full as possible. Understanding the pipeline is understanding where the ceiling comes from and why bubbles cost what they do — each bubble is a cycle the pipe did not advance.

The pipeline is also the lens for system-level timing analysis and debug. Because the structure is fixed (address leads data by one, phases overlap), an engineer reading a capture knows exactly what to expect each cycle and can spot deviations — a data phase that does not follow its address, an overlap that is broken by a bubble, a control signal that does not align with its data. So the two-phase pipeline is the reference against which timing correctness is judged, not just performance. Protocol checkers and timing-aware verification encode this structure. This is why the module treats the pipeline as the central reference: it is simultaneously the performance ceiling, the interoperability contract, and the correctness reference for AHB timing.

So at the system level, the two-phase pipeline is the timing contract every component honours, the source of the performance ceiling, and the reference for timing correctness — the structural foundation that the rest of Module 5 examines in detail.

6. Engineering Tradeoffs

The pipeline's tradeoffs were largely covered as architecture (chapter 2.5); here they are framed as timing choices.

• Two-phase pipeline vs single-cycle transfers. A registered two-stage structure gives decode time and throughput (overlap) at the cost of a one-cycle latency per transfer (data is always a cycle after address). For a stream, this latency is hidden (the pipe is full); for a single isolated access, it is a real one-cycle cost. AHB accepts the per-access latency for the streaming throughput — the right trade for a performance bus.
• One-cycle offset vs deeper pipeline. AHB uses a shallow, two-stage pipeline (one cycle of offset). A deeper pipeline could allow a higher clock but would add latency and complexity (more stages to manage, more hazards). The two-stage depth is a sweet spot: enough to decode and pipeline, shallow enough to keep latency and complexity low. AHB chooses simplicity.
• Separate buses (overlap) vs shared bus (no overlap). The overlap requires separate address and data buses (more wires). A shared bus would save wires but prevent the overlap, halving throughput. AHB spends the wires for the overlap — the same trade as the separate-data-bus choice (chapter 3.7).
• Fixed structure vs flexible timing. The rigid "address now, data next cycle" structure is less flexible than a fully handshaked, variable-timing scheme, but its fixedness is exactly what makes timing predictable, components interoperable, and waveforms readable. AHB chooses the fixed, predictable structure — flexibility is provided where needed by HREADY (wait states), not by varying the pipeline.

The throughline: the two-phase pipeline trades a one-cycle per-access latency and some wires for decode time, streaming throughput, and predictable, interoperable timing. Its shallowness keeps it simple; its fixedness keeps it legible. These are the deliberate choices that make AHB timing both performant and easy to reason about — the foundation the module builds on.

7. Industry Example

Trace a stream of transfers through the pipeline to see the structure and its performance.

A processor reads a run of words from memory — a stream of back-to-back transfers.

• The pipe fills. Cycle 1: the processor presents address A (address phase of transfer A); no data yet. Cycle 2: data A returns (data phase of A) and the processor presents address B (address phase of B) — the overlap begins. The pipe is now full.
• One transfer per cycle. From cycle 2 on, each cycle completes one transfer: data A in cycle 2, data B in cycle 3, data C in cycle 4… The processor sustains one word per cycle — the full-pipe rate — because the address phase of each transfer overlaps the data phase of the previous one. This is the pipeline delivering peak throughput.
• Reading the capture diagonally. On cycle 3, the address bus shows C and the data bus shows DB — two different transfers. To follow transfer B, you read its address on cycle 2 and its data on cycle 3 — diagonally. An engineer reading this capture tracks each transfer's address-then-data flow across the one-cycle offset, not down a single column.
• The latency on an isolated access. Now contrast a single isolated read: address A in cycle 1, data A in cycle 2 — done. The data came one cycle after the address (the pipeline latency), and there was no overlap to hide it because there was no following transfer. So the isolated access pays the one-cycle latency that the stream hides. This is the latency-vs-throughput trade made concrete: streams hide the latency, isolated accesses pay it.
• A bubble's cost. If the processor went IDLE for a cycle mid-stream, that cycle would advance no transfer — a bubble below the one-per-cycle ceiling. The pipeline defines the ceiling; bubbles are the gap to it. Reading the capture, the bubble is visible as a cycle where the diagonal address-then-data flow pauses.

The stream shows the pipeline's behaviour: it fills, then delivers one transfer per cycle by overlapping phases, with each transfer read diagonally across the one-cycle offset. The isolated access shows the latency the streaming hides, and the bubble shows the gap to the ceiling. This is the two-phase pipeline as the timing reference for everything that follows.

8. Common Mistakes

9. Interview Insight

The two-phase pipeline is foundational interview material — and the diagonal-read insight separates real understanding.

The answer that lands gives the structure, the overlap, and the timing-reference point: "Every AHB transfer is two phases one cycle apart — an address phase that describes the access, then a data phase the next cycle that moves the data, with a register between them. Because the address and data phases use different parts of the bus, consecutive transfers overlap — the next transfer's address phase runs during the current one's data phase — so once the pipe is full, one transfer completes per cycle. And critically, this structure is the timing reference for the whole protocol: address leads data by one cycle, so on any cycle the address bus and data bus belong to different transfers — you read a transfer diagonally, address now and data next cycle." The diagonal-read insight and the timing-reference framing are the senior signals.

10. Practice Challenge

Reason from the address-now-data-next-cycle frame.

1. State the structure. Describe the two phases, their one-cycle offset, and the register between them.
2. Explain the overlap. In two sentences, explain why consecutive transfers overlap and give one transfer per cycle.
3. Read diagonally. From Figure 2, follow transfer B: state the cycle of its address phase and the cycle of its data phase.
4. Latency vs throughput. Explain why a stream hides the pipeline latency but an isolated access pays it.
5. Catch the mistake. A colleague reads address A and data DB on the same cycle as one transfer. Explain the error and the correct (diagonal) reading.

11. Key Takeaways

• The two-phase pipeline is AHB's defining timing structure: an address phase, then a data phase one cycle later, with a register between them — address now, data next cycle.
• Consecutive transfers overlap (the address phase of one runs during the data phase of the previous), giving one transfer per cycle once the pipe is full — because the phases use different parts of the bus.
• On any cycle, the address and data buses belong to different transfers — read a transfer diagonally (address on cycle N, data on cycle N+1), never vertically.
• Pipelining raises stream throughput, not single-transfer latency — each transfer still has its one-cycle address-to-data offset; streams hide it, isolated accesses pay it.
• The pipeline rests on two hardware facts: a register stage (the offset, which also gives decode time) and separate address/data buses (the overlap).
• It is the timing reference for the whole protocol — the interoperability contract, the performance ceiling (one transfer/cycle), and the correctness reference that the rest of Module 5 examines.

12. What Comes Next

You now have the timing frame. The next chapters examine it in detail, starting with the one-cycle lead precisely:

• 5.2 — Address Phase Leads Data Phase (coming next) — the one-cycle offset shown exactly, and why the data phase is always the cycle after the address phase.
• 5.3 — Control / Data Alignment (coming soon) — how the address-phase control aligns with the following data phase.

To revisit the architecture origins of the pipeline, see Pipelined Operation, The Address / Control Phase, and The Data Phase; for the separate buses that enable the overlap, see HWDATA & HRDATA. For the broader protocol map, see the AMBA family overview.