Write Strobes in Bridges

Chapter 9.5 derived the active byte lanes from HSIZE and the address. This chapter follows that information downstream: how AHB's implied byte lanes become explicit per-byte write strobes in the interfaces AHB connects to. AHB itself has no explicit write-strobe signal — it implies the active lanes from HSIZE + the low address bits (a slave derives them, chapter 9.2/9.5). But downstream interfaces use explicit per-byte write strobes: APB4's PSTRB, a memory's byte-write-enables, AXI's WSTRB. So a bridge (AHB-to-APB, AHB-to-memory, AHB-to-AXI) must derive those write strobes from the AHB size and address — computing the lane-active mask and driving it as per-byte strobes. This implied-to-explicit translation is essential for correct sub-word writes downstream: only the active bytes must be written. It's a concrete, practical application of the lane-selection rule in real bridge design.

1. What Is It?

Write strobes are explicit per-byte write-enable signals — one bit per byte lane, indicating which bytes of a write are valid (to be written). The key contrast:

• AHB has no explicit write-strobe signal — it implies the active byte lanes from HSIZE + the low address bits (chapter 9.2/9.5); a slave derives the lanes itself.
• Downstream interfaces use explicit write strobes — APB4's PSTRB, a memory's byte-write-enables (BWE), AXI's WSTRB — one bit per byte, set for the active bytes.

So a bridge is where the translation happens: it computes the lane-active mask from the AHB HSIZE + address (the same derivation as chapter 9.5) and drives that mask as the downstream interface's per-byte write strobes. A word write → all strobes set; a halfword write → two strobes (for the active lanes); a byte write → one strobe (for the addressed lane). So the bridge converts AHB's implied byte lanes into explicit write strobes — making the active-byte information that AHB carries implicitly into the explicit signal the downstream interface needs.

2. Why Does It Exist?

This translation exists because AHB and its downstream interfaces represent the same active-byte information differently — AHB implicitly (HSIZE + address), downstream explicitly (per-byte strobes) — so a bridge connecting them must convert between the two representations.

AHB's choice to imply the active lanes (from HSIZE + address) keeps the AHB signal set lean — no separate strobe signal; the slave derives the lanes. This works within AHB because every AHB slave knows how to derive lanes from HSIZE + address (chapter 9.5). But downstream interfaces chose to make the active bytes explicit (per-byte strobes) — APB4's PSTRB, memory BWE, AXI's WSTRB — because explicit strobes are simpler for the downstream component to consume (it just uses the strobe bits directly, no derivation). So the two sides represent the same information (which bytes are active) in different forms. A bridge must convert AHB's implicit form (HSIZE + address) into the downstream explicit form (strobes). The translation exists because of this representational difference.

The reason the downstream explicit strobes are needed for correct sub-word writes is the same as the byte-write-enable role (chapter 9.2): a sub-word write (byte, halfword) must modify only its bytes downstream, leaving the others unchanged. The downstream interface uses the per-byte strobes as byte-write-enables — writing only the strobed bytes. So the strobes are essential for the downstream component (a memory, an APB peripheral) to do sub-word writes correctly. If the bridge didn't derive and drive the strobes — if it just wrote all bytes — sub-word writes would corrupt the neighboring bytes downstream. So the translation exists to carry the active-byte information to the downstream component, so it can write only the right bytes. The strobes are how the downstream interface knows which bytes to write.

The reason this is a bridge's job (not handled elsewhere) is that the bridge is the boundary between the AHB representation (implied) and the downstream representation (explicit). The AHB side delivers HSIZE + address (implied lanes); the downstream side needs strobes (explicit). So the bridge — sitting at the boundary — is the natural place to do the conversion: derive the lane-active mask from the AHB inputs, drive it as the downstream strobes. So the translation is a defining function of such bridges: they convert not just the protocol handshake but also the byte-lane representation (implied → explicit strobes). This is a concrete, essential part of bridge design — getting the strobes right so sub-word writes work downstream.

3. Mental Model

Model the translation as a clerk who receives an order described by "size and starting position" and fills out an explicit checklist of which items to pack — the upstream form is a description, the downstream form is a checkbox list, and the clerk converts one to the other.

An order comes in described compactly: "a halfword starting at position 2" (the AHB form — size + address). But the packing station downstream needs an explicit checklist: a row of checkboxes, one per byte position, with the relevant ones ticked (the downstream strobes — per-byte enables). So the clerk (the bridge) reads the compact description ("halfword at position 2"), works out which positions it covers (positions 2 and 3), and ticks those checkboxes on the downstream checklist (sets strobes for lanes 2–3). The packing station then packs exactly the ticked items (writes exactly the strobed bytes). The clerk converts the compact "size + position" description into the explicit checkbox list — and if the clerk got it wrong (ticked the wrong boxes), the wrong items would be packed (wrong bytes written).

This captures the translation: the compact "size + position" description = AHB's HSIZE + address (implied lanes); the explicit checkbox list = the downstream per-byte write strobes; the clerk working out and ticking the boxes = the bridge deriving the lane-active mask and driving the strobes; packing exactly the ticked items = writing exactly the strobed bytes downstream. The bridge converts the implied description into the explicit checklist.

Watch a bridge derive strobes:

The model's lesson: the bridge converts AHB's implied size+address into an explicit per-byte strobe checklist. In the waveform, the bridge derives 1111 (word), 0011 (halfword@0), 0100 (byte@2) — one strobe bit per active byte lane — from HSIZE + the offset. The downstream component writes exactly the strobed bytes.

4. Real Hardware Perspective

In hardware, the bridge's strobe-derivation logic is the same lane-active-mask decode as chapter 9.5 — taking HSIZE + the low address bits — with its output wired to the downstream interface's per-byte strobe signal.

The strobe derivation is the lane-active-mask decoder (chapter 9.5): from HSIZE (giving the size S) and the low address bits (giving the offset), it produces a per-byte mask (S active bits from the offset). The bridge wires this mask to the downstream strobe signal — APB4's PSTRB, the memory's byte-write-enables, or AXI's WSTRB. So the bridge reuses the lane-derivation logic, just routing its output to the downstream strobe port. In hardware, this is a small, direct addition to the bridge: the lane decoder feeding the strobe output. The bridge thus carries the active-byte information from AHB's implicit form to the downstream explicit form.

The downstream consumers use the strobes as byte-write-enables:

A memory uses the strobes as per-byte write enables — writing only the strobed bytes (so a byte write modifies one byte). APB4 has PSTRB (added in APB4 precisely for this — earlier APB had no byte strobes, limiting sub-word writes). AXI has WSTRB (per-byte write strobes on the write data channel). So each downstream interface consumes the strobes to do sub-word writes correctly. The bridge's job is to provide these strobes from the AHB access. Without the bridge deriving them, the downstream component couldn't do sub-word writes (it wouldn't know which bytes are valid).

The APB4 case is a notable example: classic APB (APB2/APB3) had no byte-strobe signal, so sub-word writes to APB peripherals were problematic (you'd write the whole word, or the peripheral had to handle it specially). APB4 added PSTRB to fix this — explicit per-byte write strobes. So an AHB-to-APB4 bridge derives PSTRB from the AHB HSIZE + address, enabling correct sub-word writes to APB4 peripherals. This is a concrete reason the translation matters: APB4's PSTRB is driven by the bridge from the AHB access. So the bridge's strobe derivation is what makes AHB-to-APB4 sub-word writes work — a real, common case.

A hardware note on reads: write strobes are for writes (they indicate which bytes to write). For reads, the downstream component typically returns the full word (or the relevant bytes), and the bridge/master selects the needed bytes (using the same lane info). So strobes are a write-side concept; reads use the lane info on the master side to pick the right bytes. So the bridge's strobe derivation is specifically for the write path — converting AHB's implied write lanes into downstream write strobes. (The read path uses the lane info to select bytes from the returned data.)

5. System Architecture Perspective

At the system level, write-strobe derivation is a bridge responsibility essential for correct sub-word writes across interface boundaries — connecting AHB's implied-lane model to the explicit-strobe model of APB4, memory, and AXI — and it's a concrete instance of the lane-selection rule's practical importance.

The cross-interface correctness is the system stake: a system has AHB masters writing to peripherals (often via APB), memory, or AXI subsystems — all of which need to do sub-word writes correctly (write a byte without corrupting neighbors). The bridge's strobe derivation carries the active-byte information across the boundary, so the downstream component writes the right bytes. So at the system level, the strobe derivation is what makes sub-word writes work across interface boundaries — a common, essential operation (writing a byte-wide register through an AHB-to-APB bridge, for instance). Without it, sub-word writes across bridges would corrupt data. So it's a correctness-critical bridge function in any system with mixed interfaces.

The APB4 PSTRB is the prime system example: most systems connect slow peripherals via an AHB-to-APB bridge (chapter 1.4 / Module 15). With APB4 (which added PSTRB), the bridge derives PSTRB from the AHB access, enabling correct byte/halfword writes to APB4 peripherals. So a system with APB4 peripherals relies on the bridge's strobe derivation for sub-word register writes. This is why APB4 added PSTRB and why bridges derive it — sub-word peripheral writes are common (writing individual control/status bytes). So the strobe derivation is a key part of the AHB-to-APB bridge that connects the high-performance bus to the peripheral bus.

The general principle is that interface boundaries must translate the byte-lane representation, not just the protocol handshake. A bridge does both: it converts the protocol (AHB handshake ↔ APB/AXI handshake) and the byte-lane representation (AHB implied lanes ↔ explicit strobes). So a complete bridge design must handle the strobe derivation, not just the handshake conversion. This is a common gap — focusing on the handshake and forgetting the strobes — which would break sub-word writes. So at the system level, the lesson is that bridge design includes byte-lane/strobe translation as a first-class concern. The lane-selection rule (chapter 9.5) is what the bridge computes; the strobe derivation is its practical application at every interface boundary. So write-strobe derivation connects the abstract lane rule to concrete, correctness-critical bridge design across the system's interface boundaries.

6. Engineering Tradeoffs

Write-strobe derivation reflects AHB's implied-lanes vs downstream's explicit-strobes representations.

• Implied lanes (AHB) vs explicit strobes (downstream). AHB implying the lanes (HSIZE + address) keeps the AHB signal set lean, at the cost that each slave derives the lanes. Downstream explicit strobes are simpler for the consumer (use directly) but add a signal. The bridge converts between them — each representation suits its side.
• Bridge derives strobes vs downstream derives. Having the bridge derive the strobes (and downstream consume them directly) puts the derivation at the boundary, where the conversion is needed. The alternative (passing HSIZE+address downstream for it to derive) would require the downstream interface to do AHB-style derivation, which it isn't built for. The bridge derives — it's the boundary.
• APB4 PSTRB vs no strobes. APB4 adding PSTRB enables correct sub-word writes (vs classic APB's no-strobe limitation) at the cost of the PSTRB signal. The benefit (correct byte/halfword peripheral writes) is worth it — which is why APB4 added it.
• Reuse the lane decoder vs separate logic. The bridge reusing the lane-active-mask decoder (chapter 9.5) for the strobes is economical — same logic, routed to the strobe output. Separate strobe logic would duplicate it. Reuse is efficient.

The throughline: a bridge derives explicit per-byte write strobes from AHB's implied byte lanes (HSIZE + address), driving the downstream interface's strobe signal (APB4 PSTRB, memory byte-write-enables, AXI WSTRB). This carries the active-byte information across the interface boundary, enabling correct sub-word writes downstream (write only the active bytes). It's a concrete application of the lane-selection rule, a correctness-critical bridge function, and the reason APB4 added PSTRB. Bridge design must include this byte-lane/strobe translation, not just the protocol handshake.

7. Industry Example

Trace write-strobe derivation through bridges in a system.

A system has AHB masters connecting to APB4 peripherals (via an AHB-to-APB4 bridge) and to memory.

• A byte write to an APB4 peripheral register. The processor writes one byte to a byte-wide control register on an APB4 peripheral, via the AHB-to-APB4 bridge. The bridge derives PSTRB from the AHB access: HSIZE=byte + the address → a strobe with one bit set (for the addressed byte lane). It drives this PSTRB to the APB4 peripheral, which writes only that byte. So the byte write reaches the peripheral correctly, modifying one byte. The bridge's PSTRB derivation made the sub-word write work.
• A halfword write to a 16-bit field. A halfword write to a peripheral's 16-bit register: the bridge derives PSTRB with two bits set (the active lanes), and the peripheral writes those two bytes. Again, the strobe derivation carries the active-byte info.
• A word write. A word write to a 32-bit register: PSTRB with all four bits set; the peripheral writes the whole word. The full-width case.
• Why PSTRB matters (classic APB contrast). Had this been classic APB (no PSTRB), the bridge couldn't convey which bytes to write — a byte write would be problematic (write the whole word, corrupting the other bytes, or require special peripheral handling). APB4's PSTRB fixed this, and the bridge derives it. So the system's correct sub-word peripheral writes depend on APB4's PSTRB and the bridge's derivation of it.
• A sub-word write to memory. A byte write to a 32-bit memory (directly or via a bridge): the byte-write-enables (derived from HSIZE + address) enable one byte, so the memory writes one byte and preserves the others. The same strobe-derivation principle, for memory's byte-write-enables.
• A bridge bug avoided. If the AHB-to-APB4 bridge had been designed without PSTRB derivation (only converting the handshake), byte/halfword writes to APB4 peripherals would corrupt neighboring register bytes — a real bug. Deriving PSTRB correctly avoids it. So the bridge's strobe derivation is essential and easy to overlook.

The example shows write-strobe derivation in practice: the AHB-to-APB4 bridge derives PSTRB from the AHB HSIZE + address, enabling correct byte/halfword/word writes to APB4 peripherals (vs classic APB's limitation), and the same principle drives memory byte-write-enables. The strobe derivation carries the active-byte info across the boundary, making sub-word writes correct — a critical, easily-overlooked bridge function.

8. Common Mistakes

9. Interview Insight

Write strobes in bridges is a practical interview topic — the implied-to-explicit translation and the APB4 PSTRB example are the signals.

The answer that lands explains the representational difference and the bridge's role: "AHB doesn't have an explicit write-strobe signal — it implies the active byte lanes from HSIZE and the low address bits, and a slave derives them. But downstream interfaces use explicit per-byte write strobes: APB4 has PSTRB, a memory has byte-write-enables, AXI has WSTRB. So a bridge connecting AHB to one of these must derive the write strobes from the AHB size and address — it computes the lane-active mask, the same way a slave would, and drives it as the downstream strobe signal, one strobe bit per active byte lane. A word write sets all the strobes, a halfword two, a byte one. This is essential for correct sub-word writes downstream — the downstream component uses the strobes as byte-write-enables, so a byte write modifies only its byte without corrupting the neighbors. A great example is APB4: classic APB had no byte strobes, so sub-word writes were problematic; APB4 added PSTRB, and an AHB-to-APB4 bridge derives PSTRB from the AHB access. The key point is that a bridge must translate not just the protocol handshake but also the byte-lane representation — implied lanes to explicit strobes — or sub-word writes break." The implied-to-explicit translation, the bridge's derivation, and the APB4 PSTRB example are the senior signals.

10. Practice Challenge

Reason from the strobe derivation.

1. State the difference. Explain how AHB and downstream interfaces represent the active bytes differently.
2. Derive strobes. Give the write strobe (per-byte) for a word, a halfword at offset 2, and a byte at offset 1 on a 32-bit bus.
3. The bridge's role. Explain what a bridge does to enable sub-word writes downstream.
4. APB4. Explain why APB4 added PSTRB and how the bridge uses it.
5. A bug. Describe what breaks if a bridge omits strobe derivation.

11. Key Takeaways

• AHB has no explicit write-strobe signal — it implies the active byte lanes from HSIZE + the low address bits (the slave derives them).
• Downstream interfaces use explicit per-byte write strobes — APB4 PSTRB, memory byte-write-enables, AXI WSTRB.
• A bridge derives the strobes — it computes the lane-active mask (HSIZE + address, chapter 9.5) and drives it as the downstream strobe, one bit per active byte lane.
• This is essential for correct sub-word writes downstream — the downstream component uses the strobes as byte-write-enables, writing only the active bytes (so a byte write doesn't corrupt neighbors).
• APB4 added PSTRB to enable sub-word writes (classic APB had no byte strobes); an AHB-to-APB4 bridge derives PSTRB from the AHB access.
• A bridge must translate the byte-lane representation, not just the protocol handshake — forgetting the strobes breaks sub-word writes (a real, easily-overlooked bug).

12. What Comes Next

You now understand how AHB's implied lanes become downstream write strobes. The final chapter of the module covers narrow transfers:

• 9.8 — Narrow Transfers (coming next) — sub-bus-width transfers and their lane behavior, closing the size-and-alignment module.

To revisit the lane derivation the strobes come from, see Lane Selection and Byte, Halfword & Word Transfers. For the bridge that does this translation, see Master, Slave, Decoder & Arbiter. For the broader protocol map, see the AMBA family overview.