AMBA APB · Module 2

The Address Phase (Setup)

The SETUP phase of an APB transfer — PSEL asserted with PENABLE low while address, control, and write data become visible and must stay stable into the access phase.

Every APB transfer opens with a single, deliberate cycle: SETUP, the address phase. This is where the subordinate is selected, where the access is presented, and where — crucially — the manager makes a promise about stability that the rest of the transfer depends on. The overview told you SETUP exists; this chapter is about what makes a SETUP correct. The single idea to carry: SETUP is one cycle in which the access becomes visible and is locked stable, and getting that lock right is what keeps the whole transfer honest.

1. What problem is being solved?

The problem is giving the subordinate an unambiguous cycle to see the access and prepare for it, before anything is committed.

A subordinate cannot act on an access the instant the address changes — it has to decode that address, decide whether it is the target, and ready its read mux or write enable. If the manager presented the access and committed in the same edge, the subordinate would have no settled cycle to do that work, and combinational decode would have to race the commit. APB solves this by carving out one dedicated cycle up front:

The subordinate is selected. PSEL goes high so the targeted subordinate knows a transfer aimed at it has begun.
The access is presented. PADDR, PWRITE, and (for writes) PWDATA become valid together — the what of the transfer is now on the bus.
Nothing is committed yet. PENABLE is held low, marking this cycle as preparation, not action.

That cycle — PSEL high, PENABLE low, the access valid and stable — is the SETUP phase. Its whole job is to hand the subordinate a clean, settled view of the access one cycle before the access is performed.

2. Why the previous mental model is not enough

The transfer overview said, correctly, that "SETUP happens first." That is true but not sufficient, because knowing SETUP happens does not tell you what makes a SETUP correct — and an incorrect SETUP corrupts the transfer while the lifecycle still looks perfectly legal.

The overview answers "what is the order of phases?" It does not answer the two questions that decide whether the transfer is actually valid: what must be true during SETUP, and what must keep being true after it. Two substantive rules live here, and neither is visible from the high-level sequence:

The PENABLE-low decode window is the substance of SETUP, not a formality. SETUP is defined by PSEL high and PENABLE low. That low PENABLE is the signal that says "presented, not committed" — it is the cycle the subordinate uses to decode and prepare. Skip the distinction and you cannot explain why APB needs SETUP at all.
The stability contract outlives SETUP. The values presented in SETUP — address, direction, write data — must remain stable not just through SETUP but all the way through ACCESS until the transfer completes. A waveform can show the correct IDLE → SETUP → ACCESS walk and still be broken if those values wobble mid-transfer.

So the overview gives you the position of SETUP in the sequence; this chapter gives you the contract SETUP enforces. The position is easy; the contract is where real designs go wrong.

3. APB transfer mental model

The model: SETUP is the moment you place an order at a counter and the cashier reads it back before charging you.

You step up and put the full order on the counter — what you want, and the payment if you are paying (the access: address, direction, write data). The cashier needs one beat to read it and ring it up; nothing is charged yet (PENABLE low — the decode window). And here is the part that matters: once your order is on the counter, you do not change it while it is being processed. Swapping the order mid-transaction is how you get charged for one thing and handed another. SETUP places the order and freezes it; ACCESS is the charge.

Three refinements make the model precise:

One cycle to read the order. SETUP is exactly one cycle. The subordinate gets that single settled cycle to decode; APB never lingers in SETUP and never skips it.
PENABLE low means "not yet committed." While PENABLE is low the access is merely presented. The transition to PENABLE high is the move from "order placed" to "order being charged" — from SETUP to ACCESS.
The order stays frozen until done. Whatever was presented in SETUP must hold stable through ACCESS until completion. Changing the address, direction, or write data mid-transfer is the protocol equivalent of swapping your order after the cashier started ringing it up.

Figure 1 — the SETUP cycle against PCLK. In the SETUP cycle PSEL goes high to select the subordinate while PENABLE stays low, and PADDR, PWRITE, and PWDATA become valid together — the access is now presented. This single PSEL-high, PENABLE-low cycle is the subordinate's window to decode the address and prepare its response. SETUP lasts exactly one cycle; one cycle later PENABLE goes high and the transfer enters ACCESS, where the access is actually performed. The diagram emphasises that the presented values become valid in SETUP and that SETUP always immediately precedes ACCESS.

4. Real SoC / hardware context

In hardware, SETUP is the cycle the manager (the APB bridge) drives to open a transfer, and the cycle the subordinate spends decoding. The two sides have complementary jobs in this one cycle, and both are deliberately cheap.

On the manager side, entering SETUP means driving PSEL for the targeted subordinate high, placing the address and control onto the bus, placing write data for a write — and holding PENABLE low. The bridge has just translated a fast-bus access into APB terms, and SETUP is where it presents that access. Because SETUP is unconditional and one cycle, the manager's logic is trivial: present, then advance.

On the subordinate side, SETUP is the cycle its address decoder does its work. A typical subordinate decodes PADDR against its register map to select which register the access targets, and sets up its write enable or read mux accordingly — all combinationally or registered off this cycle, so that by the time PENABLE rises the subordinate is ready to act or to drive PREADY. This is precisely why the access must be stable: the decoder is staring at PADDR and PWRITE, and if they moved, the decode would be invalid.

The stability requirement is not a soft guideline — it is the load-bearing rule of the address phase. The manager must hold PADDR, PWRITE, and PWDATA (and PSEL) constant from the moment they are presented in SETUP through every ACCESS cycle until PREADY is sampled high. During a wait state, when ACCESS stretches because the subordinate held PREADY low, the manager simply keeps holding everything stable and waits. Nothing the manager presented in SETUP is allowed to change until the lifecycle says the transfer is done.

Figure 2 — the stability contract. Top (legal): the values presented in SETUP — PADDR, PWRITE, PWDATA — are held as one unchanging value across SETUP and every ACCESS cycle, including a wait-state cycle where PREADY is low, right up to completion when PREADY is high; the subordinate decodes and captures the correct access. Bottom (illegal): the same signals are changed mid-transfer during an ACCESS cycle before completion, which corrupts the access — the subordinate may decode or capture the wrong thing. The rule is that the access presented in SETUP must remain stable through ACCESS until PREADY is high, and changing it mid-transfer is a protocol violation.

5. Engineering tradeoff table

The address phase is a set of deliberate choices. Each spends a little to buy the subordinate a clean, safe window.

SETUP design choice	What it gives up	What it buys	Why it is correct for APB
A dedicated one-cycle SETUP	A cycle of latency per transfer	A settled decode/prepare window before commit	Latency is free for sparse control traffic
`PENABLE` low to mark "presented, not committed"	A separate "valid" handshake	A single bit that distinguishes preparation from action	One marker reused; trivial logic on both sides
Access held stable SETUP → completion	Freedom to retime address/data	A decode that stays valid for the whole transfer	A wobbling access would corrupt decode and capture
No SETUP-skipping fast path	A possible one-cycle transfer	One legal entry into every transfer	Simplicity and verifiability beat a saved cycle
Same SETUP for reads and writes	Direction-specialized timing	One uniform address phase	`PWRITE` carries direction; the phase shape need not

The throughline: SETUP spends one cycle and one stability promise to give the subordinate certainty about what is being accessed before anything is performed. That certainty is what the elastic ACCESS phase then builds on.

6. Common RTL / architecture / waveform mistakes

Misconceptions to unlearn

"The transfer is committed as soon as the address appears in SETUP." No. In SETUP the access is only presented. PENABLE is low precisely to say "not committed yet." The access is performed in ACCESS, and completes only when PREADY is high.
"SETUP can last more than one cycle." No. SETUP is always exactly one cycle; the move to ACCESS is unconditional. Only ACCESS stretches (via PREADY), never SETUP.
"PENABLE and PSEL go high together at the start." No. In SETUP PSEL is high while PENABLE is low — that gap is the whole point of the phase. PENABLE rises one cycle later, to mark ACCESS.
"Once SETUP ends, the address and data can change." No. The access presented in SETUP must stay stable through ACCESS until PREADY is high — including across wait states. Changing it mid-transfer corrupts the access.
"During a wait state the manager can update the address for the next access." No. While PREADY is low the transfer is still in ACCESS; the manager holds everything stable. The next access is presented only in a fresh SETUP after this one completes.
"Reads and writes have different setup phases." No. SETUP looks the same for both; PWRITE simply indicates the direction, and PWDATA is meaningful only for writes. The phase structure is identical.

7. Interview framing

A common APB question is "walk me through the start of a transfer" or "what exactly happens in the SETUP cycle?" It probes whether you treat SETUP as a real protocol phase with a contract, or just as "the cycle the address shows up."

The strong answer names the three facts of SETUP in order: PSEL goes high to select the subordinate while PENABLE stays low; the access — address, direction, and write data — becomes valid together; and SETUP lasts exactly one cycle, the subordinate's window to decode and prepare. Then volunteer the depth point that separates you: the values presented in SETUP must stay stable through ACCESS until completion, because the subordinate's decode of PADDR and PWRITE is only consumed when the access commits — change them mid-transfer and you corrupt it even though the lifecycle still looks legal. What interviewers are really checking is whether you understand why PENABLE is low in SETUP (the decode window) and why stability matters (valid decode through commit) — the difference between reciting signals and understanding the contract.

8. Q&A

9. Practice

State the signature. From memory, write the exact condition that defines the SETUP cycle in terms of PSEL and PENABLE, and say how many cycles it lasts.
List what is presented. Name the three things that become valid in SETUP and state which one is meaningful only for writes.
Trace the hold. For a transfer with two wait states, state across how many cycles PADDR and PWRITE must be held stable, and which signal's value finally releases them.
Spot the bug. A manager presents an address in SETUP, then changes PADDR during an ACCESS cycle in which PREADY was low. Explain which rule it broke and what the subordinate might do wrong.
Explain the gap. In one or two sentences, explain why PENABLE is low during SETUP and what that low value tells the subordinate to do.

10. Key takeaways

SETUP is the address phase of an APB transfer — PSEL high while PENABLE is low — and it is a real protocol phase with a contract, not just the cycle the address appears.
The access is presented, not committed, in SETUP. PADDR, PWRITE, and (for writes) PWDATA become valid together; the low PENABLE marks this as preparation, and the access is performed only in ACCESS.
SETUP lasts exactly one cycle and is never skipped. It is the subordinate's guaranteed window to decode the presented access and prepare its response before the access commits.
The presented values must stay stable from SETUP through ACCESS until completion — including across wait states — because the subordinate's decode is only consumed when the access commits on PREADY high.
Changing the access mid-transfer is a protocol violation even when the IDLE → SETUP → ACCESS walk looks correct; the lifecycle can look right while a wobbling address corrupts the transfer.
SETUP looks the same for reads and writes — PWRITE carries the direction and PWDATA matters only for writes; the phase structure is uniform, which is what keeps both manager and subordinate logic trivial.