AMBA APB · Module 6

Read Waveform Analysis

A repeatable six-move method for reading any APB read waveform — locate the request, find the access, count the PREADY-low waits, land on the completion edge, read PRDATA there, and check PSLVERR — applied to fast, slow, and error reads.

Module 6 gave you the read rules one signal at a time: the subordinate drives PRDATA, the value is valid only at completion, PREADY paces the round trip, and PSLVERR reports failure. This capstone converts those rules into a skill — a fixed, repeatable method for reading any APB read waveform from left to right and saying exactly what value the manager captured, or that it captured nothing trustworthy at all. The single idea to carry: you read a read waveform by following the round trip, not by scanning signals — locate the request, find the access, count the waits, land on the one completion edge, read PRDATA there, and check PSLVERR before you trust it. The same six moves read a fast read, a slow read, and a broken one.

1. What problem is being solved?

The problem is turning a read's waveform rows into one precise answer — which cycle is the data real, and may I trust it — the same way every time, whether the read is instant, stalled, or failed.

A read waveform is a handful of rows (PSEL, PENABLE, PWRITE, PADDR, PRDATA, PREADY, PSLVERR) over a few cycles, and a beginner draws the wrong conclusion by reading them in the wrong order. They see PENABLE high and say "the data is here" — but PENABLE is high across every wait cycle, while PRDATA is still in transit. They grab PRDATA at the first access cycle — but on a slow read that is a don't-care. They read the value and never glance at PSLVERR — and consume a number the subordinate flagged as garbage. The fix is a fixed reading order that maps each waveform feature to a read fact:

PSEL high with PWRITE low → the request. This is a read being launched; the manager is asking, not writing.
PENABLE rising → the access boundary. The round trip's return leg starts; PENABLE then stays high for the whole access, waits included.
PREADY → the cadence and the completion edge. PREADY-low access cycles are waits where PRDATA is don't-care; the first PREADY-high access cycle is the one completion edge.
PRDATA and PSLVERR at completion → the answer and its validity. PRDATA is read only on the completion edge, and only trusted if PSLVERR is low there.

Read in that order and every read interprets itself — and every broken one fails a specific step.

Figure 1 — a fully annotated fast zero-wait APB read walked IDLE to IDLE against PCLK with the full read signal set. In IDLE, PSEL is low. SETUP raises PSEL and presents PADDR with PWRITE low — the request, a read, is out but nothing has returned. ACCESS raises PENABLE; the fast subordinate drives PREADY high on that same cycle, so PSEL, PENABLE, and PREADY are all high on the single completion edge, marked with a dashed line, where PRDATA is valid and the manager captures it. PSLVERR is low across the transfer, so the captured value is trusted. PRDATA is shown don't-care in IDLE, SETUP, and the early access, and valid only at completion. Every key edge is labelled: the request, the PWRITE-low read direction, the PENABLE rise into access, the single completion edge, and the captured value.

2. Why the previous model is not enough

You arrive here with the read flow as a round trip, PRDATA timing telling you the value is valid only at completion, the PREADY interaction pacing the waits, and read error responses telling you PSLVERR flags a bad read. Each is a rule. None of them, by itself, is a procedure — and an engineer in front of an unfamiliar read waveform, or a broken one, needs a procedure, not a list of facts.

The gap is three-fold:

The rules are unordered; reading must be ordered. Knowing the four read facts does not tell you which to apply first. Check PRDATA before you have located the completion edge and you cannot even say which cycle's value counts. The request and the access must be located before the data can be judged.
The rules describe one read; waveforms vary. A rule says "PRDATA is valid at completion." A real read might insert zero, one, or many wait cycles, so "find completion" is a search, not a fixed cycle. The method has to be wait-count-agnostic.
The rules assume a good read; debugging starts from a broken one. Every rule above is stated for a successful read. Debugging means reading a waveform where PSLVERR is high, or PRDATA was sampled early, or the read never completes — and you need the same method to localise which step failed, turning Module 6's read rules into a reading method and a debugging tool for a read that came back wrong.

So the model to add is not another signal rule. It is the discipline of reading a read: a fixed six-move pass that takes the read rules you already know and makes them a method you can run on any read waveform, fast, slow, or failed.

3. Mental model

The model: read a read waveform like tracing a question to its answer — find where the question was asked, follow it to where the answer arrives, take the answer there, and check it is not stamped "invalid." The request is the question, the access is the wait at the counter, the completion edge is the moment the answer is handed over, and PSLVERR is the "rejected" stamp you check before you believe it.

Picture scanning the waveform left to right with six moves on a card, asked in order. You do not stare at all the rows at once; you locate the request, then the access, then walk the access cycles counting waits, then land on the completion edge, then read PRDATA there, then check PSLVERR. By the time you reach the last move you have already drawn the one cycle the data is real, so reading and trusting it is trivial — you know exactly where to look and what could disqualify it.

Three refinements make the method precise:

Request first, access second, completion by search. Locate PSEL high with PWRITE low (this is a read) and the PENABLE rise (access begun) before searching for completion, because the completion search is only meaningful inside the access phase. The first PREADY-high access cycle is completion; the PREADY-low ones before it are waits, and PRDATA is don't-care across them.
PRDATA is read once, at the handoff. The returned value is real on exactly one cycle — the completion edge. Sampling it during setup or a wait latches in-transit garbage. There is no "early peek."
PSLVERR is the final gate. A read can complete normally — PREADY high, one clean completion edge — and still hand back invalid data with PSLVERR high. Trusting PRDATA without checking PSLVERR on the same edge is consuming a number the subordinate already disowned.

4. Real SoC / hardware context

In practice you run this method on a simulation waveform or a logic-analyser capture during bring-up, and the three reads below are the cases you will read constantly: the fast read (a register that answers immediately), the slow read (a source across a clock domain or behind a FIFO that inserts backpressure), and the error read (an unmapped or faulted address). Reading all three with the same six moves is the whole point — the method does not change, only the wait count and the PSLVERR value do.

The slow read. The reading is identical to the fast read up to the wait count, where it diverges: PENABLE is held high across three access cycles, PREADY is sampled low on the first two — those are the wait states, where PRDATA is don't-care — and high only on the third. The completion search therefore lands on the third access cycle as the single completion edge, and that is the only cycle PRDATA is valid and read. PADDR and PWRITE are held byte-for-byte across all of access, waits included; the round trip's return leg simply took longer. PSLVERR is low, so the value is trusted.

Figure 2 — a fully annotated slow APB read with two wait states, read with the same method against PCLK. The phase bands read IDLE, SETUP, then ACCESS spanning three cycles labelled WAIT, WAIT, COMPLETE. PSEL rises into SETUP with PWRITE low, then PENABLE rises and is held high across all three access cycles. PREADY is sampled low on the first two access cycles — the two wait states where PRDATA is don't-care, in transit — and high only on the third, the single completion edge marked with a dashed line, where PRDATA becomes valid and the manager captures it. PADDR and PWRITE are held stable across the entire access phase as one continuous band. PSLVERR is low, so the captured value is trusted. The figure labels the two wait cycles, the don't-care PRDATA during the waits, and the one completion edge — showing the method is unchanged from the fast read, only the wait count differs.

The error read. The first five moves run exactly as on the fast read: request located, access found, no waits, one completion edge with PREADY high — the read completes, it is not retried and does not hang. The sixth move is where it breaks: on that completion edge PSLVERR is high. The transfer is finished and the bus moves on, but the returned PRDATA is invalid and must be discarded, not consumed. This is exactly why the last move exists: a read that completes is not the same as a read whose data you may trust.

Figure 3 — a fully annotated error APB read against PCLK. The phase bands read IDLE, SETUP, ACCESS COMPLETE ERROR, IDLE. PSEL rises into SETUP with PWRITE low, then PENABLE rises into the single access cycle and the subordinate drives PREADY high — so the transfer completes normally on one completion edge, not retried and not hung. But on that same completion edge PSLVERR is high, signalling an error response, and PRDATA is marked not-to-be-trusted: benign and discarded, because PSLVERR high means the read data is invalid. The dashed completion marker is drawn in red, and the annotations stress two facts: the transfer still completes on the single completion edge where PSEL, PENABLE, and PREADY are all high, and the returned read data is invalid because PSLVERR is high — so it is discarded, not consumed.

5. Engineering tradeoff table

The six-move method is a deliberate reading discipline. Each move trades a tempting shortcut for a reading that stays correct on every read — fast, slow, or failed.

Reading move	The shortcut it rejects	What it buys	Why it is correct for an APB read
Locate the request by `PSEL` high + `PWRITE` low	"Start where the address appears"	A real read, identified as a read	`PSEL` high is the protocol start; `PWRITE` low confirms direction
Locate access by `PENABLE` rise	"`PENABLE` high means data is here"	The access boundary, separated from completion	`PENABLE` is high across waits, while `PRDATA` is still in transit
Find completion by first `PREADY`-high	"`PRDATA` is good at the first access cycle"	Correct reading at any wait count	The subordinate owns how long the return leg takes
Read `PRDATA` only at completion	"Sample `PRDATA` whenever it looks settled"	One unambiguous capture cycle	`PRDATA` is don't-care everywhere but the completion edge
Check `PSLVERR` before trusting	"It completed, so the data is good"	A read you may actually consume	A read can complete and still return invalid data

The throughline: by reading request and access first, finding completion by search, and gating trust on PSLVERR, the method is immune to the three things that vary across reads — wait-state count, whether the data arrives fast or slow, and whether the read succeeded — so the same six moves cover the fast read, the slow read, and the error read.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"PRDATA is valid as soon as PENABLE is high." No. PENABLE is high across the whole access phase, every wait cycle included, while PRDATA is still in transit (don't-care). PRDATA is read only on the completion edge — the first PREADY-high access cycle, found by search.
"A slow read returns its data during the wait cycles." No. During PREADY-low waits PRDATA is don't-care; the value becomes valid only on the single completion edge. Sampling it mid-wait latches garbage.
"If the read completed, the data is good." No. A read can complete normally — one clean completion edge with PREADY high — and still carry PSLVERR high. That value is invalid and must be discarded; completion and trust are two separate checks.
"A multi-wait read has several cycles where I could read PRDATA." No. There is exactly one — the first PREADY-high access cycle. Every PREADY-low access cycle before it is a wait with don't-care PRDATA.
"PSLVERR high means the read got retried or hung." No. On an error read PREADY still goes high and the transfer completes in the normal two phases; PSLVERR high only marks the data invalid — the bus does not stall or retry on APB.
"A different read needs a different reading approach." No. The six moves, in order, read every APB read — fast, slow, or error. Inventing a new approach per waveform is how you misread one.

Figure 4 — classifying a read with the six-move method: a legal read (top, green) versus an illegal ready-before-data read (bottom, red), both with one wait state. In the legal read, PREADY stays low while PRDATA is don't-care and rises only on the cycle PRDATA becomes valid, so move 5 — read PRDATA at completion only if it is valid — passes and the manager captures a good value. In the illegal read, PREADY rises on the first access cycle while PRDATA is still don't-care, so the subordinate signalled completion before its data was ready; the manager captures don't-care data and move 5 fails. The figure teaches that an illegal read fails exactly one move, which both names the bug and points to the side that owns it — here the subordinate, which must tie PREADY to data-ready.

Debugging scenario — is this read legal or a bug? classify it

Observed symptom: during bring-up a captured read waveform "looks almost right," and you must decide whether to accept it or reject it as a subtle protocol bug — guessing is how bad reads ship.
Waveform clue: run the six moves on it; an illegal read fails exactly one. In Figure 4 the bottom read fails move 5 — PREADY is high but PRDATA is still don't-care on that edge, so the "completion" hands back invalid data. Other failures look the same way: PRDATA changing after the completion edge, or PSLVERR high with the data treated as valid.
Root cause: localised by which move fails — move 4/5 (ready-before-data or early sample) is a data-validity bug; the failing move also names the owner: a PREADY-vs-PRDATA mismatch is subordinate-side, an early capture is manager-side.
Fix / habit: never eyeball a read as "close enough" — classify every read by the six-move method, and the one move that fails is your bug, your assertion, and the block to fix. A clean read passes all six; reject anything that does not.

7. Interview framing

Interviewers test this by sliding a read waveform across the table and asking "what value did the manager capture — and may it trust it?" The weak candidate points at PRDATA at the first access cycle; the strong one runs a visible, ordered method and narrates each move. Demonstrating the procedure is the answer.

Say it as the six-move pass: find PSEL high with PWRITE low — that is a read request; find where PENABLE rises — that is access; walk the access cycles and the PREADY-low ones are waits where PRDATA is don't-care; the first PREADY-high access cycle is the single completion edge; read PRDATA on exactly that edge; then check PSLVERR on the same edge before trusting it. The depth signal that lands: state that the method is identical for zero waits and ten — completion is found by searching for the first PREADY-high cycle, not by a fixed position — and that the final PSLVERR gate separates "the read completed" from "the read data is valid," which is precisely the bug a sloppy capture misses. An interviewer hears a repeatable engineering method, not memorised trivia.

8. Q&A

9. Practice

Run the six moves. Take the fast read (Figure 1) and write the answers in order: where the request is (PSEL high, PWRITE low), where access begins, how many PREADY-low waits, which cycle is completion, what PRDATA is there, and whether PSLVERR clears it.
Re-run on the slow read. Do the same for Figure 2 and confirm only the wait-count answer differs from the fast read — and state what PRDATA is on each of the two wait cycles.
Gate on PSLVERR. For the error read (Figure 3), state which of the six moves the read passes, which one it fails, and what the manager must do with PRDATA.
Find the early-sample bug. A manager latches PRDATA on the first cycle PENABLE is high, ignoring PREADY. On the slow two-wait read, name which move it skips, which cycle it wrongly samples, and what it captures.
Localise the bad read. Given a read waveform where PREADY and PRDATA look normal but the consuming logic gets wrong data intermittently, name the move most likely skipped and the signal it checks.

10. Key takeaways

Read a read waveform by following the round trip, not by scanning signals — locate the request, find the access, count the waits, land on the one completion edge, read PRDATA there, then check PSLVERR, always in that order.
The request is PSEL high with PWRITE low, and the access begins at the PENABLE rise — PENABLE then stays high across the whole access phase, waits included, while PRDATA is still in transit.
Find completion by searching, not by position — the first access cycle where PSEL, PENABLE, and PREADY are all high is the single completion edge; the PREADY-low access cycles before it are waits with don't-care PRDATA.
Read PRDATA on exactly one cycle — the completion edge. Everywhere else it is in-transit don't-care, so an early sample latches garbage.
The method is wait-count-agnostic. Fast read or ten-wait read, the same six moves apply identically; only the count of PREADY-low cycles differs.
PSLVERR is the final gate — a read can complete on a clean completion edge and still return invalid data with PSLVERR high. Completion and trust are separate checks; skip the gate and you consume an error response as data.