AMBA AXI · Module 1

AXI vs AHB vs APB

A mechanism-level comparison of the three classic AMBA buses — APB, AHB, and AXI — across handshake, pipelining, concurrency, bandwidth, and cost.

The previous chapter placed the AMBA protocols on a map. This one puts the three classic memory-mapped buses — APB, AHB, and AXI — side by side and compares how they actually move a transfer. The goal is not to crown a winner; it is to make the trade-offs concrete enough that, shown any of the three, you can explain its transfer model, predict its bandwidth ceiling, and say why an architect chose it there. We compare at the mechanism level — phases, pipelining, concurrency, cost — and still hold the channel-signal detail for later modules.

1. Three Buses, One Decision

APB, AHB, and AXI are all memory-mapped AMBA buses: a master issues an address and reads or writes data at a slave. They differ in how much machinery they put between "I want to move data" and "the data moved." That machinery buys concurrency and bandwidth — and costs logic, verification effort, and design time. Comparing them is really comparing how much of that machinery a given piece of traffic actually needs.

Three questions separate them, and they are the spine of this chapter:

How is a single transfer structured? (the handshake / phase model)
How many transfers can be in flight at once? (pipelining and concurrency)
What does that cost? (logic area, complexity, verification)

Get those three and the right-bus-for-the-job answer falls out on its own.

2. APB — The Two-Phase Peripheral Bus

APB moves one transfer as two phases: a setup phase that presents the address and control, then an access phase that completes the read or write (optionally extended with wait states). There is no pipelining and no concurrency — the next transfer cannot begin until the current one finishes. That is by design: APB exists for configuration registers and slow peripherals, where transfers are rare and the priority is minimal logic, not throughput.

The payoff is that an APB slave is almost trivial to build and verify. The price is a hard, low bandwidth ceiling — which, for a baud-rate register touched once at boot, is no price at all.

3. AHB — The Pipelined Shared Bus

AHB keeps a single shared bus but pipelines it: the address phase of the next transfer overlaps the data phase of the current one, so the bus is busier than APB's strict two-phase march. It adds bursts (a sequence of related transfers from one address handshake) and arbitration so multiple masters can take turns.

Its ceiling is structural, and it is the exact gap Chapter 1.1 described: the bus is shared and held. A granted master owns the bus for its transfer, the pipeline is only one stage deep, and the system still does essentially one transfer in flight at a time. Pipelining overlaps address and data; it does not let two independent transactions progress at once. That is enough for a simple single-master subsystem and not enough for a chip full of concurrent high-bandwidth masters.

4. AXI — The Decoupled Multi-Channel Interconnect

AXI replaces "one shared, held bus" with independent paths for requesting, moving data, and responding, routed through a switch-like interconnect. Because those paths are decoupled, a master can keep many transactions outstanding, responses can return out of order, and two masters talking to two slaves proceed in parallel rather than taking turns. Bursts move blocks of data efficiently on top of that.

This is more machinery: more wires, more states, a far larger verification surface. AXI earns it on the CPU-to-memory and DMA-to-memory paths where concurrency and latency-hiding decide system performance — and it is overkill on a GPIO register, which is precisely why real chips keep APB around for those.

Figure 1 — the transfer model of each bus, time flowing left to right. APB marches two phases per transfer with no overlap; AHB overlaps the next address with the current data on one shared bus (one transfer in flight); AXI decouples address, data, and response so many transactions overlap freely. The deeper the overlap, the higher the achievable throughput — and the more machinery required.

5. Side by Side — The Mechanism Comparison

The contrast across the axes that matter, without oversimplifying any single one:

Aspect	APB	AHB	AXI
Transfer model	Two phases (setup, access), serial	Pipelined address + data on a shared bus	Independent address / data / response paths
Transfers in flight	One, no overlap	One (pipelined a single stage deep)	Many outstanding, out of order
Concurrency	None	Masters arbitrate and take turns	Parallel master→slave conversations
Bursts	No	Yes	Yes (and longer / more flexible)
Bandwidth ceiling	Low	Moderate	High
Topology	Simple bus behind a bridge	Shared bus + arbiter	Switch / interconnect
Coherency	No	No	No — plain AXI; ACE/CHI add it
Logic & verification cost	Very low	Moderate	High
Natural home	Control / config registers	Simple, mostly single-master subsystems	High-performance masters + memory

Read the table as a single story: each column to the right adds the ability to overlap more work, and pays for it in complexity. Nothing in the table says "newer is better" — it says "more capable where you need it, more expensive where you don't."

The same single access, expressed as how each bus thinks:

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Snippet

// Conceptual — one access, three styles of thinking (not implementations).
// APB : present address, then data — one transfer, finish before the next.
//         access(addr, data);                       // serial
// AHB : pipeline the next address over the current data on a shared bus —
//         addr(a0); data(a0) || addr(a1);           // one transfer in flight
// AXI : issue many requests without waiting; responses return in any order.
//         req(a0); req(a1); req(a2);                // outstanding + out-of-order

Three altitudes of concurrency in three lines — and the entire performance gap between the buses lives in that last one.

6. Pipelining & Concurrency — Where the Bandwidth Comes From

The single biggest performance separator is how many transactions can make progress at once, and it is worth isolating because beginners conflate it with clock speed or bus width.

APB has no overlap: phase, phase, done, repeat. Throughput is one transfer per (setup+access) window.
AHB overlaps adjacent transfers by one stage and adds bursts, so the shared bus stays busier — but the chip is still doing one transaction's worth of work in flight, and a slow slave or a busy bus stalls everyone waiting their turn.
AXI keeps many transactions outstanding and lets their responses return independently, so memory latency is hidden behind other in-flight work and disjoint traffic runs truly in parallel.

This is why "just make AHB faster" doesn't reach AXI-class throughput: a faster or wider shared bus still serializes. The win is concurrency, a property of the protocol model, not a clock-frequency knob.

Figure 2 — concurrency depth. APB does one transfer with no overlap; AHB keeps one transfer in flight with a one-stage pipeline; AXI keeps many transactions outstanding with out-of-order completion. Bandwidth scales with this depth, which is why a faster shared bus never matches a decoupled one.

7. Cost & Complexity — Why Heavier Isn't Always Better

The comparison is incomplete if it only counts bandwidth, because capability has a price and a good architect spends it deliberately. AXI's outstanding transactions, out-of-order completion, and interconnect routing are real gate count, real timing-closure effort, and a verification space that is orders of magnitude larger than APB's. Putting AXI on a handful of status registers buys nothing and pays all of that cost.

So the three buses occupy three points on a capability-vs-cost curve, and the right choice is the cheapest bus that meets the traffic's need — not the most capable one available.

Figure 3 — capability versus cost. The three buses sit at three points on the same curve: APB is cheap and low-bandwidth, AHB is the moderate middle, AXI is high-capability and high-cost. The engineering goal is the cheapest bus that meets the need — over-provisioning wastes area, power, and verification effort.

8. Choosing Between Them

In practice the choice is a short series of questions about the traffic, not about the protocols' prestige. Work top-down: start from the cheapest bus and only step up when a real requirement forces you to.

Figure 4 — a practical selection flow. Start cheap and climb only when a requirement demands it: registers stay on APB; a simple single-master subsystem is fine on AHB-Lite; concurrent high-bandwidth masters need AXI. (Coherency between caching masters pushes you to ACE/CHI — see the previous chapter.)

9. Common Misconceptions

Myths to unlearn

"AXI is always faster than AHB, so use AXI." AXI is faster when concurrency is the bottleneck. On a single-master subsystem with no concurrent traffic, AXI's machinery sits idle while you pay its area and verification cost — AHB-Lite delivers the same useful throughput for far less.
"Pipelining (AHB) and concurrency (AXI) are the same thing." No. AHB's pipeline overlaps the phases of adjacent transfers on one shared bus — still one transaction in flight. AXI keeps many independent transactions outstanding in parallel. Different mechanisms, different ceilings.
"Bigger bus width or higher clock closes the gap to AXI." It raises a shared bus's peak but not its concurrency. A serialized bus stays serialized; latency is still paid with the bus occupied.
"APB is obsolete." APB is the correct choice for control registers and still ships in current designs. Cheapness is a feature, not a legacy wart.
"They're three versions of one bus." They are three distinct protocols with different transfer models and costs, commonly used together in one SoC, each on the traffic it fits.

10. Debugging Insight

🔍 Debugging insight — the transfer model tells you what 'stuck' even means

When a transfer hangs, the first useful question is which bus am I on, because each bus's transfer model defines a different failure shape:

On APB, there is one transfer and two phases — a hang is almost always the access phase not completing (a slave holding wait states forever, or a missing/!ready completer). The search space is tiny.
On AHB, the bus is pipelined and shared, so a stall is usually an arbitration problem (a master never granted) or a wait-state problem rippling back through the one-deep pipeline. You look at who holds the bus and who is waiting for it.
On AXI, transfers are decoupled and many are outstanding, so "stuck" usually means a handshake or dependency problem on one of the independent paths, or an outstanding transaction whose response never returns. You reason about which path stalled and which in-flight transaction is missing its completion — a fundamentally different (and larger) hunt.

Naming the bus first tells you whether you are looking for one slow access, one ungranted master, or one missing response among many — and stops you from applying APB intuition to an AXI bug.

11. Verification Insight

✅ Verification insight — the bus sets the size of the test problem

The transfer model also sets how big a verification job you have signed up for:

APB — a small, bounded job: address decode, read/write data integrity, wait-state handling, register access rules. Largely directed, with a modest state space.
AHB — adds arbitration fairness and pipelined-transfer correctness: grant behaviour, address/data-phase overlap, bursts, wait states. The state space grows with masters and burst types.
AXI — a much larger job: outstanding transactions, ordering, out-of-order completion, and backpressure across independent paths. This is where constrained-random stimulus, protocol assertions, and scoreboards stop being optional, because the legal-but-stressful interleavings are too many to enumerate by hand.

The practical takeaway: pick the verification approach to match the bus's concurrency, not the other way around. The detailed techniques arrive in the verification module; here, just size the problem correctly.

12. Interview Questions

13. Summary

APB, AHB, and AXI are three memory-mapped AMBA buses that differ in how a transfer is structured and how many transfers can be in flight at once. APB runs one two-phase transfer at a time — cheap, serial, perfect for control registers. AHB pipelines address over data on a shared, held bus and adds bursts and arbitration — moderate bandwidth, ideal for simple mostly-single-master subsystems. AXI decouples address, data, and response onto independent paths through a switch, keeping many transactions outstanding with out-of-order completion — high bandwidth for concurrent masters and memory, at a high logic and verification cost.

The unifying idea: capability climbs left-to-right and so does cost, so the right bus is the cheapest one that meets the traffic's need — not the most capable one available. Pipelining (AHB) is not concurrency (AXI); a faster shared bus does not become a decoupled one; and APB is a current, deliberate choice, not a relic. Carry the three questions — transfer model, transfers-in-flight, and cost — and you can compare these buses, and predict their behaviour, on sight.

14. What Comes Next

You can now compare the three classic buses at the mechanism level. The next chapter builds the model that the rest of the AXI track depends on:

1.4 — The AXI Mental Model (coming next) — the channel-and-transaction model AXI is built on, the foundation for every chapter after Module 1.

Previous: 1.2 — The AMBA Family Overview. For the broader protocol catalog, see the AMBA family overview doc.