AMBA AXI · Module 12

Clock & Reset in Interconnect

How an AXI interconnect handles clock-domain crossings, reset coordination, and the conversion components — clock converters, width up/downsizers, and protocol bridges — that let heterogeneous IP with different clocks, widths, and protocols interoperate.

The interconnect's third core job (Chapter 12.1) is conversion — bridging the mismatches between heterogeneous IP. Real SoCs combine masters and subordinates running at different clock frequencies, with different data widths, and even different protocol versions (AXI3/AXI4, full-AXI/AXI4-Lite/APB). The interconnect is where all this heterogeneity meets, so it contains clock-domain-crossing (CDC) bridges, width converters (up/downsizers), and protocol converters, plus careful reset coordination. This closing Module 12 chapter covers how the fabric handles clocks, resets, and conversion while preserving AXI semantics.

1. Clock-Domain Crossings

Managers and subordinates often run in different clock domains (a CPU at one frequency, a peripheral at another, memory at a third). The interconnect bridges them with clock-domain-crossing (CDC) logic — typically an asynchronous FIFO (with gray-coded pointers and synchronizers) on each channel, so data safely crosses from one clock to another without metastability.

AXI's VALID/READY handshake makes CDC tractable: each channel is a simple flow-controlled stream, so an async FIFO per channel (AW, W, B, AR, R) cleanly decouples the two domains — the source clocks data into the FIFO, the destination clocks it out, and the handshake provides the back-pressure. The cost is latency (synchronizer stages add cycles) and buffering (the FIFOs), which feeds the outstanding depth needed to sustain throughput across the crossing (Chapter 8.1). A related, cheaper case is synchronous rate conversion — two domains with a known integer clock ratio (e.g., 2:1) bridged without full async synchronization.

Figure 1 — clock-domain crossing. The manager and subordinate run in different clock domains; the interconnect places CDC logic (an async FIFO per channel, with gray-coded pointers and synchronizers) between them. AXI's per-channel VALID/READY handshake makes this clean — each channel crosses independently. The crossing adds latency and buffering.

2. Reset Coordination

Reset (ARESETn, active-low) must be handled carefully in an interconnect because transactions can be in flight when a reset asserts. Resetting one part of the fabric while outstanding transactions exist can leave dangling state — a manager waiting for a response that will never come, or an outstanding-transaction tracker out of sync.

Key reset concerns: AXI requires synchronous deassertion (reset releases cleanly relative to the clock) to avoid metastability on release; and a reset must either quiesce in-flight transactions first (drain or cleanly abandon them) or reset coordinated domains together so no half-reset state results. In a multi-clock interconnect there are also multiple reset domains (one per clock domain), and resetting them independently while transactions cross between them is hazardous — the reset strategy must account for the crossings (e.g., reset the CDC FIFOs and both sides consistently). So reset isn't a trivial "clear everything" — in a fabric with outstanding transactions and multiple domains, it requires a deliberate sequence.

Figure 2 — reset coordination. With transactions in flight and multiple clock/reset domains, resetting carelessly leaves dangling outstanding state (a manager awaiting a response that never returns). Reset must use synchronous deassertion, quiesce in-flight transactions or reset coordinated domains together, and handle the CDC crossings consistently — a deliberate sequence, not a blind clear.

3. Width Conversion

When a manager and subordinate have different data widths (e.g., a 128-bit manager and a 32-bit peripheral), the interconnect uses a width converter:

Downsizer (wide → narrow): a wide beat is split into multiple narrow beats (a 128-bit write becomes four 32-bit beats), and the burst/length adjusted accordingly. Reads reassemble narrow responses into wide ones.
Upsizer (narrow → wide): multiple narrow beats are packed into a wide beat (four 32-bit beats → one 128-bit beat), improving efficiency to a wide subordinate.

The converter must preserve everything: the data bytes, WSTRB (which bytes are valid, re-mapped to the new width), burst semantics (the resized burst covers the same bytes — recall the address-calculation byte map of 7.5), IDs (for response routing), and ordering. It adds latency and buffering (packing/unpacking takes cycles). Width conversion is essentially the byte-accurate re-packetization of a transaction across a width boundary, and getting the WSTRB/byte mapping right is the critical correctness concern (the stream analog was TKEEP, 11.4).

Figure 3 — width conversion. A downsizer splits each wide beat into multiple narrow beats (128→32 bit: one beat becomes four); an upsizer packs multiple narrow beats into a wide one. The converter must preserve data, WSTRB byte validity (re-mapped to the new width), burst semantics, IDs, and ordering — byte-accurate re-packetization across the width boundary, adding latency/buffering.

4. Protocol Conversion

The interconnect also bridges different protocol versions/variants:

AXI3 ↔ AXI4: reconcile the AxLEN width (4-bit vs 8-bit — a long AXI4 burst must be split to ≤16 beats for AXI3, Chapter 7.1), the removed locked access (AxLOCK 2-bit vs 1-bit, Chapter 9.4), and AXI3's separate WID (write data ID) which AXI4 dropped.
Full-AXI ↔ AXI4-Lite: a full master talking to a Lite slave issues only single-beat, single-ID transactions; a converter restricts/adapts accordingly (Chapter 10.1).
AXI ↔ APB / AHB: bridge to the simpler buses — the AXI-to-APB bridge (Chapter 10.3) translates AXI single-beats into APB 2-phase transfers (mapping responses SLVERR↔PSLVERR, handling wait states).

Each protocol converter must preserve the transaction's intent across the boundary — same data, same byte semantics, correctly mapped responses and ordering — while adapting the signaling. These converters (plus width and clock converters) are why heterogeneous IP can share one fabric: the interconnect absorbs the differences in one place rather than forcing every IP to match every other. Each adds latency/buffering, contributing to the system's overall latency budget.

Figure 4 — protocol conversion bridges variants: AXI3↔AXI4 (AxLEN width, locked removal, WID), full-AXI↔AXI4-Lite (single-beat restriction), and AXI↔APB/AHB (e.g., AXI-to-APB 2-phase translation). Each converter preserves the transaction's data/byte/response semantics while adapting signaling — concentrating heterogeneity in the interconnect so any IP can connect to any other.

5. Common Misconceptions

Myths to unlearn

"All IP on the interconnect runs at one clock." Often not — managers/subordinates run in different clock domains, bridged by CDC logic (async FIFOs) in the interconnect. The handshake makes this clean but it adds latency.
"Reset just clears everything instantly." In a fabric with outstanding transactions and multiple reset domains, careless reset leaves dangling state — reset needs synchronous deassertion and quiescing/coordination, a deliberate sequence.
"Width conversion just changes the bus width." It re-packetizes the transaction (split/pack beats) and must preserve data, WSTRB byte validity, burst semantics, IDs, and ordering — byte-accurate, not just a width relabel.
"AXI3 and AXI4 are interchangeable across a bridge." They differ (AxLEN width, locked access, WID) — a converter must reconcile these (e.g., split a 256-beat AXI4 burst for AXI3).
"Converters are free." Each (CDC, width, protocol) adds latency and buffering, which interacts with the outstanding depth needed to sustain throughput (Chapter 8.1).
"Conversion changes the protocol semantics." It preserves them — same data/bytes/response/ordering — while adapting signaling. The transaction's intent crosses the boundary intact.

6. Debugging Insight

🔍 Debugging insight — boundary-specific failures point at a converter

Conversion bugs are boundary-specific — they appear only across a clock/width/protocol crossing:

Data corruption or metastability only across a clock boundary? A CDC bug — async FIFO/synchronizer issue, or a signal crossing domains without proper synchronization. Check the CDC logic on each channel.
A hang or dangling transaction after reset? A reset-coordination problem — reset asserted with transactions in flight, leaving a manager awaiting a response or the tracker out of sync. Check the reset sequence/quiescing and that domains reset consistently.
Data corruption or wrong byte placement across a width boundary? A width-converter bug — WSTRB/byte mapping wrong in the split/pack, or burst length/semantics mis-adjusted. Check the byte-accurate re-packetization (7.5/6.7).
A long burst or locked access fails across an AXI3 boundary? A protocol-converter issue — AxLEN not split to ≤16, or locked access not handled (9.4). Check the version reconciliation.
A Lite slave mishandles a burst from a full master? Missing full-AXI→Lite conversion (single-beat restriction not applied, 10.1).

The triage: corruption-across-clock → CDC; post-reset hang → reset coordination; wrong-bytes-across-width → width converter; version/feature failure → protocol converter. The signature is always that it's specific to a boundary — quiescent or same-domain traffic works, the crossing fails — which localizes the bug to that converter.

7. Verification Insight

✅ Verification insight — verify each conversion boundary preserves semantics

Each conversion type needs targeted verification that it preserves AXI semantics across the boundary. CDC: verify data integrity across clock domains at various clock-ratio and phase relationships (including extreme ratios), no metastability/loss, and correct handshake flow control through the async FIFOs. Reset: verify reset with transactions in flight leaves no dangling state — outstanding transactions are cleanly drained or abandoned, the tracker recovers, and synchronous deassertion works; test reset in each domain and coordinated. Width conversion: byte-accurate — every byte and WSTRB bit maps correctly through split/pack, burst lengths adjust correctly, IDs/ordering preserved; sweep width ratios and burst sizes (the partial/unaligned cases, 7.5/7.7). Protocol conversion: AXI3↔AXI4 (split long bursts, handle locked/WID), full↔Lite (single-beat), AXI↔APB (2-phase, response mapping) — each preserving data/response/order.

Coverage should include: every clock-ratio relationship at each CDC; reset during in-flight transactions (each domain and combined); width conversion across all ratios with aligned/unaligned/partial bursts; and each protocol-conversion boundary with the version-specific edge cases. The highest-value tests are reset-during-traffic (a notorious source of dangling-transaction bugs) and byte-accurate width conversion (where WSTRB/byte-mapping errors silently corrupt). Because these converters bridge heterogeneity, verifying that the transaction's data, bytes, responses, and ordering survive each crossing is the core check — same as the end-to-end AXI-preservation requirement (12.1), focused at each boundary.

8. Interview Questions

9. Summary

The interconnect's conversion job bridges heterogeneous IP across three kinds of mismatch, plus reset coordination. Clock-domain crossings use per-channel async FIFOs (gray-coded, synchronized) — clean thanks to the VALID/READY handshake, at the cost of latency/buffering. Reset must be a deliberate sequence (synchronous deassertion, quiesce in-flight transactions or reset coordinated domains together, handle CDC crossings) — careless reset with outstanding transactions leaves dangling state. Width converters (downsizer split / upsizer pack) re-packetize byte-accurately, preserving data, WSTRB, burst semantics, IDs, and ordering. Protocol converters bridge AXI3↔AXI4 (AxLEN width, locked removal, WID), full-AXI↔AXI4-Lite (single-beat), and AXI↔APB/AHB (2-phase, response mapping).

The unifying principle: concentrating conversion in the interconnect turns pairwise heterogeneity (O(N²)) into a single integration layer (O(N)) — each IP connects with its native clock/width/protocol and the fabric absorbs the differences, preserving AXI semantics across every boundary (adding latency that feeds outstanding-depth needs). Conversion bugs are boundary-specific (work in-domain, fail across a crossing): CDC corruption, post-reset dangling state, width byte-mapping errors, protocol-version failures — so verify each boundary preserves data/bytes/responses/ordering, with reset-during-traffic and byte-accurate width conversion as the highest-value tests. This completes Module 12 (the AXI interconnect). Next, Module 13 turns to performance — bandwidth, throughput, latency, and how to optimize them.

10. What Comes Next

You've completed the interconnect; Module 13 turns to performance:

13.1 — Bandwidth & Throughput (coming next) — defining and computing AXI bandwidth and sustained throughput, the foundation of performance analysis.

Previous: 12.6 — Multiple Managers & Subordinates. Related: 8.1 — Why Outstanding Transactions Exist for the latency/buffering interaction, and 10.3 — APB vs AXI4-Lite for the AXI-to-APB bridge. For the broader protocol catalog, see the AMBA family overview doc.