AMBA AXI · Module 9

Memory Barriers & Coherency Boundary

Where AXI's ordering model ends and cache coherency begins — why AXI provides no coherency or barrier transactions, how system-wide memory ordering is enforced, and how ACE and CHI layer coherency on top of AXI.

This chapter closes Module 9 by drawing the boundary of AXI's ordering model — the line where the protocol stops and cache-coherency protocols take over. AXI gives you a non-coherent, point-to-point ordered transport: the same-ID/same-direction ordering of 9.1, plus exclusive access for atomics. What it deliberately does not provide is cache coherency, system-wide memory barriers, or cross-master memory consistency beyond what IDs and exclusive access offer. When a system has coherent caches and needs those guarantees, it moves up a layer to ACE or CHI, which build coherency on top of (or alongside) AXI. Understanding this boundary is what separates "I know AXI" from "I know where AXI fits in a coherent SoC."

1. What AXI Does Not Provide

AXI's guarantees are intentionally minimal. Three things it does not do:

No cache coherency. AXI has no concept of coherent caches, snooping, or cache-line state. If two masters cache the same location, AXI will not keep their copies consistent — it just moves transactions.
No barrier transactions. AXI4 has no memory-barrier/fence transaction type. You cannot issue a "barrier" on the bus that orders all prior accesses against all later ones system-wide.
No cross-master consistency model. Beyond same-ID ordering (within one master's stream) and exclusive access (atomics), AXI makes no promise about the global order in which different masters' accesses become visible.

These omissions are by design — they keep AXI fast and simple as a transport. The consistency and coherency a multi-core system needs live in a higher layer.

Figure 1 — the limits of AXI's model. AXI provides ordered transport (same-ID/same-direction) and atomics (exclusive access), but NOT cache coherency, NOT barrier/fence transactions, and NOT a cross-master consistency model. These are deliberate omissions — the coherency layer above AXI supplies them.

2. The Coherency Boundary — Layering

The AMBA family layers concerns: non-coherent transport at the bottom (APB, AHB, AXI), coherency on top (ACE, CHI). AXI is the ordered point-to-point transport; when a design adds coherent caches and needs system-wide ordering, it adopts a coherency protocol that extends or replaces the AXI layer:

Below the line (transport): AXI — moves data with minimal ordering, no coherency.
Above the line (coherency): ACE / CHI — add the snooping, cache-state, and barrier machinery for a coherent, consistent shared-memory system.

The boundary is exactly where this chapter's "AXI does not provide" list gets satisfied. A master that only needs ordered access to memory stays at the AXI layer; a coherent CPU cluster sharing memory operates at the ACE/CHI layer.

Figure 2 — the AMBA layering and the coherency boundary. Non-coherent transport (APB/AHB/AXI) sits below; coherency protocols (ACE/CHI) sit above and supply snooping, cache state, and barriers. The 'coherency boundary' is where AXI's minimal ordering ends and system-wide coherency/consistency begins.

3. ACE and CHI — Coherency on Top

The two AMBA coherency protocols approach it differently:

ACE (AXI Coherency Extensions) — extends AXI. It adds snoop channels (so a cache can be asked about a line it holds), coherent transaction types, cache-line states (a MOESI-style model), and barrier and DVM (distributed virtual memory, for TLB/cache maintenance) messages. ACE is AXI plus the coherency machinery — a natural upgrade for AXI-based coherent clusters.
CHI (Coherent Hub Interface) — a newer (AMBA 5), packet/credit-based protocol designed for large, many-core, scalable systems. Rather than extending AXI's channel/handshake model, CHI uses a layered, message-based architecture suited to high core counts and complex topologies (meshes, rings). It supersedes ACE at the high end.

Both provide what AXI doesn't: the system-wide coherency and ordering (including barriers) that shared-cache multiprocessing requires. AXI remains underneath/alongside for non-coherent traffic (peripherals, DMA to non-cached regions).

Figure 3 — ACE vs CHI. ACE extends AXI with snoop channels, coherent transactions, cache states, and barrier/DVM messages — AXI plus coherency. CHI is a newer packet/credit-based protocol for large, scalable many-core systems, superseding ACE at the high end. Both supply the coherency and barriers AXI lacks.

4. Enforcing System Ordering — Where Each Lives

The practical decision: what ordering do you need, and at which layer?

Point-to-point, same-stream ordering (one master's accesses to memory in order): the AXI layer handles it — same-ID ordering plus response-waits at read/write dependencies (Module 9.1–9.2).
Atomic read-modify-write (locks, counters): AXI exclusive access (9.3) — still the AXI layer.
Cache coherency (multiple masters caching shared data consistently) or system-wide barriers/fences (order all prior accesses before later ones across the memory system): the ACE/CHI layer — above AXI.

So a master enforces what it can at the AXI layer (IDs, response-waits, exclusive), and reaches for the coherency layer only when it needs coherency or true system barriers. Knowing which guarantee lives where prevents two errors: assuming AXI gives coherency/barriers (it doesn't), and reaching for ACE/CHI complexity when AXI-layer ordering would suffice.

Figure 4 — choosing the layer for the ordering you need. Same-stream ordering and atomics live at the AXI layer (IDs, response-waits, exclusive access); cache coherency and system-wide barriers live at the ACE/CHI layer. Match the requirement to the layer — don't expect coherency from AXI, and don't add ACE/CHI where AXI ordering suffices.

5. Common Misconceptions

Myths to unlearn

"AXI keeps cached copies coherent." No — AXI has no coherency. If multiple masters cache a location, AXI won't keep them consistent; that's an ACE/CHI job.
"There's an AXI barrier/fence transaction." There isn't — AXI4 has no barrier transaction. System-wide ordering comes from the coherency layer (ACE/CHI) or from master-enforced response-waits for point dependencies.
"Same-ID ordering gives me memory consistency across masters." Same-ID ordering is within one master's stream. Global, cross-master visibility ordering is a coherency-layer concern.
"ACE and CHI are alternatives to AXI." ACE extends AXI (coherency on top); CHI is a separate, newer protocol for large systems. AXI remains the non-coherent transport beneath/alongside.
"If I use ACE/CHI I don't need AXI." Non-coherent traffic (peripherals, non-cached DMA) still uses AXI; coherency protocols handle the coherent subset.
"Coherency is always needed." Only for shared, cached data. Plenty of traffic (peripherals, private buffers, streaming) is non-coherent and stays at the AXI layer.

6. Debugging Insight

🔍 Debugging insight — 'coherency bugs' on AXI are layer mismatches

Most "AXI doesn't keep my data consistent" issues are really using the wrong layer:

Two masters see different values for a shared cached location? That's a coherency problem AXI doesn't solve — you need ACE/CHI (or to mark the region non-cacheable so there's a single copy). Expecting AXI to keep cached copies consistent is a layer error.
Expected a fence/barrier to order accesses across the system? AXI has no barrier transaction — the ordering must come from the coherency layer's barriers or, for a point dependency, a master response-wait. There's nothing on the AXI bus to "wait for."
Cross-master ordering assumption fails? AXI only orders within one master's same-ID stream; global ordering across masters needs the coherency layer. The assumption was never an AXI guarantee.
A peripheral/DMA region accidentally marked cacheable causing stale reads? A coherency/attribute issue (recall AxCACHE, 6.4) — non-coherent regions must be non-cacheable so there's one authoritative copy.

The triage: any symptom involving multiple cached copies or system-wide ordering is above AXI's pay grade — solve it at the coherency layer (ACE/CHI) or by removing the need for coherency (non-cacheable regions, single copy). AXI-layer tools (IDs, response-waits, exclusive) only address point ordering and atomics.

7. Verification Insight

✅ Verification insight — verify AXI to its boundary, coherency above it

For pure AXI verification, the scope is exactly the AXI guarantees — ordering (Module 8–9), bursts, handshakes, exclusive access — and a key negative property: confirm the design does not assume coherency or barriers from the bus (e.g., a master that needs cross-master consistency must use the coherency layer, not rely on AXI). At the AXI level, verify that non-coherent regions are correctly attributed (non-cacheable where there must be a single copy) so no false coherency expectation exists. Coherency itself — snoop correctness, cache-state transitions, barrier ordering, DVM — is verified at the ACE/CHI layer with its own (much larger) methodology, outside AXI's scope.

Coverage-wise, the AXI boundary check is mostly architectural: assert the address map's coherency/cacheability attributes match each region's intent, and that masters requiring coherency are connected through the coherency layer rather than plain AXI. The highest-value check is catching a layer mismatch — a coherency or barrier expectation placed on plain AXI — early, since it's an architectural error that no amount of AXI-level transaction testing would surface (the transactions are all individually legal; the expectation is wrong). This is the natural endpoint of AXI verification: verify AXI to its contract, and recognize when a requirement has crossed into coherency territory.

8. Interview Questions

9. Summary

AXI's ordering model has a deliberate boundary: it provides a non-coherent, point-to-point ordered transport — same-ID/same-direction ordering plus exclusive atomics — and nothing more. It does not provide cache coherency, barrier/fence transactions, or a cross-master consistency model. Those live a layer up, in ACE (which extends AXI with snoop channels, cache states, and barrier/DVM messaging) and CHI (a newer packet/credit-based protocol for large many-core systems). The coherency boundary is exactly where AXI's omissions get satisfied by the upper layer: non-coherent transport (APB/AHB/AXI) below, coherency (ACE/CHI) above.

The design discipline is to match the guarantee to the layer: point ordering and atomics at the AXI layer (IDs, response-waits, exclusive access); cache coherency and system barriers at the ACE/CHI layer. Most "AXI doesn't keep my data consistent" bugs are layer mismatches — expecting coherency or barriers from a transport that never promised them — fixed by moving to the coherency layer or removing the need for coherency (non-cacheable regions). AMBA layered it this way because coherency is the exception, not the rule, so the transport stays lean and pays for coherency only where data is truly shared. This completes Module 9 and the core AXI protocol; the next modules cover the AXI variants — starting with AXI4-Lite, the simplified subset.

10. What Comes Next

You've reached the edge of AXI's model; the next module turns to the protocol's variants:

10.1 — Why AXI4-Lite Exists (coming next) — the single-beat, no-burst simplified subset for control/register access, and why it exists.

Previous: 9.4 — Locked Access (Legacy AXI3). Related: 9.1 — Read & Write Ordering for the ordering this chapter bounds, and 6.4 — AxLOCK & AxCACHE for cacheability attributes. For the broader protocol catalog, see the AMBA family overview doc.