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AMBA AXI · Module 4

Write Transaction Waveforms

Annotated end-to-end AXI write waveforms — single-beat, burst, and stalled — assembling AW, W (WSTRB/WLAST), and B (BRESP) into one readable picture.

This chapter assembles everything in Module 4 into the picture you'll actually face on a logic analyzer or simulator: the end-to-end write waveform. We walk three canonical shapes — a single-beat write, a burst write, and a stalled write (backpressure on the data phase) — annotating each handshake so you can read AW, W (WSTRB/WLAST), and B (BRESP) at a glance. Then we distill a repeatable method for reading any write waveform. This is the Critical capstone of the write path: master these three pictures and you can debug a write on sight.

1. The Whole Write, Assembled

A write is three handshakes in sequence: AW launches it (address + shape), W delivers the data beats (WDATA/WSTRB, ending in WLAST), and B confirms it (BRESP). On a waveform you read it by finding those three transfer events — AWVALID && AWREADY, each WVALID && WREADY (with WLAST on the last), and BVALID && BREADY — and checking they agree: the W-beat count matches AWLEN+1, and the BRESP says it landed. The three shapes below are the same transaction under different conditions.

2. The Single-Beat Write

The simplest case: one address, one data beat, one response.

valid / ready (per channel)

Single-beat write — AW → W (WLAST) → B

12 cycles
A single-beat write: awvalid and awready transfer the address, then wvalid, wready and wlast transfer the one data beat, then bvalid, bready and bresp=OKAY transfer the response.address (AW)data (W)response (B)awaddr acceptedawaddr acceptedwdata acceptedwdata acceptedbresp acceptedbresp acceptedaclkawvalidawreadyawaddrXX0x200x20XXXXXXXXwvalidwreadywdataXXXX0xA50xA5XXXXXXwlastbvalidbreadybrespXXXXXXXXOKOKXXt0t1t2t3t4t5t6t7t8t9t10t11
AWLEN=0 (one beat); WLAST asserts on that single W beat; BRESP=OKAY on B completes the write.
Figure 1 — a single-beat AXI write. The address transfers on the AW handshake; the one data beat transfers on the W handshake with WLAST=1 (single beat); then the subordinate returns BRESP=OKAY on the B handshake. The write completes only when B is accepted. Three handshakes, AWLEN=0, one beat.

This is the baseline every other write is built from. AWLEN=0, so the single W beat carries WLAST=1, and the lone BRESP closes it. Note again that the data going out (the W handshake) does not finish the write — only accepting B does.

3. The Burst Write

Now one address launches multiple data beats. AW is accepted once; the W channel then streams AWLEN+1 beats, asserting WLAST on the last; finally one B response covers the whole burst.

Burst write — one AW, four W beats, one B

10 cycles
AW handshake at cycle 2 for a 4-beat burst; four W data beats D0 to D3 on cycles 2 to 5 with WLAST on D3; then a single B response with BRESP OKAY accepted at cycle 8.W data phase — 4 beatsAW accepted (AWLEN=3 → 4 beats)AW accepted (AWLEN=3 →…WLAST on D3 — data phase endsWLAST on D3 — data pha…B=OKAY — write completeB=OKAY — write completeaclkawvalidawreadyawaddrX0x200x20XXXXXXXwvalidwreadywdataXXD0D1D2D3XXXXwlastbvalidbreadybrespXXXXXXXOKOKXt0t1t2t3t4t5t6t7t8t9
Figure 2 — a 4-beat burst write (AWLEN=3) end to end. AW is accepted at cycle 2 (address 0x20, 4-beat burst). The W channel delivers D0–D3 on cycles 2–5, with WLAST on D3 (cycle 5). After the data is accepted, the subordinate drives BVALID with BRESP=OKAY, accepted at cycle 8 — one response for the whole burst. The W-beat count (4) equals AWLEN+1.

Read it as the three phases: AW (cycle 2), the W burst (cycles 2–5, four beats, WLAST on the fourth), then B (cycle 8). The single BRESP covers all four beats — there is no per-beat write response. The gap between WLAST (cycle 5) and B (cycle 7–8) is the subordinate's processing latency, which is legal and unbounded (4.5).

4. The Stalled Write — Backpressure on the Data Phase

Real subordinates aren't always ready. Here the subordinate backpressures the W channel mid-burst by dropping WREADY; the manager holds WVALID and the data stable (stability rule) until it rises again.

Stalled write — backpressure on W

11 cycles
AW accepted at cycle 2; the W channel transfers D0, then WREADY drops for cycles 4 and 5 while the manager holds WVALID and D1 stable; D1 transfers at cycle 6, then D2 with WLAST, then BRESP OKAY on B.WREADY low — backpressure (D1 held)D0 transfersD0 transfersWREADY drops → stall, D1 held stableWREADY drops → stall, …WREADY back → D1 then D2 (WLAST)WREADY back → D1 then …aclkawvalidawreadywvalidwreadywdataXXD0D1D1D1D2XXXXwlastbvalidbreadybrespXXXXXXXXOKOKXt0t1t2t3t4t5t6t7t8t9t10
Figure 3 — a stalled burst write. After AW is accepted, the subordinate drops WREADY for cycles 4–5 (backpressure); the manager holds WVALID and D1 stable across the stall, and D1 transfers only when WREADY returns at cycle 6. The remaining beats follow, WLAST closes the burst, and B=OKAY completes it. The stall inserts bubbles but loses nothing.

The tell of a healthy stall: WVALID stays high and WDATA is unchanged (here D1 held) across the low-WREADY window, and the beat transfers the moment WREADY returns. Nothing is lost — the bubbles just lower throughput. Contrast with the dropped-VALID bug (3.6), where WVALID would illegally fall during the stall.

5. How to Read Any Write Waveform

The three shapes share one reading method — a repeatable sequence that turns a wall of signals into a verdict:

Method: find AW handshake and read the shape; count W beats to WLAST and check equals AWLEN+1; inspect WSTRB per beat; read B's BRESP and BID.1. Find AWhandshake readAWADDR, AWLEN,AWSIZE, AWBURST2. Count W beats toWLAST must = AWLEN+13. Check WSTRB perbeat which byteswritten4. Read B BRESP= success? BID =which write
Figure 4 — the write-waveform reading method. Find the AW handshake (get the shape), count the W beats to WLAST (must equal AWLEN+1), check WSTRB on each beat (which bytes), then read B (BRESP for success, BID for pairing). Each step checks one channel against what AW declared.

In words: AW gives the contract; W and B are checked against it. Get AWLEN from AW, count W beats to WLAST (they must match), confirm WSTRB selects the intended bytes, then read BRESP for the verdict and BID to pair it. Every write bug from Module 4 shows up as a step that disagrees — wrong beat count, mis-placed WLAST, ignored/wrong WSTRB, a non-OKAY BRESP, or a mismatched BID.

6. Common Misconceptions

7. Debugging Insight

8. Verification Insight

9. Interview Questions

10. Summary

A write on a waveform is three handshakes to find and reconcile: AW (the contract — address and AWLEN/AWSIZE/AWBURST), the W burst (exactly AWLEN+1 beats, WSTRB per beat, WLAST on the last), and B (one BRESP, paired by BID). The three canonical shapes are the same transaction under different conditions: the single-beat write (AWLEN=0, one beat, one response), the burst write (one AW, many beats, one B, with a legal unbounded gap before B), and the stalled write (backpressure on W, with WVALID/WDATA held stable across the stall — lossless).

Read any of them with one method: find AW, count W to WLAST (= AWLEN+1), check WSTRB, read BRESP/BID — and every Module 4 bug surfaces as the step that disagrees. Verify with these shapes as the floor, crossed with partial strobes, error responses, independent backpressure, and outstanding/out-of-order writes. That completes the write path; Module 5 does the same channel-by-channel walk for the read path, beginning with the AR channel.

11. What Comes Next

That closes Module 4 — Write Transactions. Module 5 walks the read path the same way:

Previous: 4.5 — BRESP & Write Response Timing. For the broader protocol catalog, see the AMBA family overview doc.