Concurrent vs Sequential Statements

1. Engineering intuition — two worlds, one bridge

Think of the architecture body as a board: everything placed on it — gates, sub-blocks, processes — runs at once, in parallel, and the order you draw them does not matter. That is the concurrent world. Inside one of those blocks, you sometimes want to describe behaviour as a recipe: "do this, then if that, then this" — an ordered sequence. That is the sequential world, and it lives inside a process. The process is the bridge: from the outside it is one parallel block; on the inside it reads top to bottom.

2. Formal explanation — where each kind of statement lives

The two categories are defined by where they may appear:

architecture rtl of demo is
begin
  -- CONCURRENT world (architecture body): parallel, order-independent
  y   <= a and b;                       -- concurrent signal assignment
  u   <= entity work.sub port map (...);-- instance
  gen : for i in ... generate ...       -- generate
  proc : process (clk)                  -- a process is ONE concurrent statement...
  begin
    -- SEQUENTIAL world (inside the process): ordered, top to bottom
    if rising_edge(clk) then            -- if statement (sequential)
      q <= d;                           -- sequential signal assignment
    end if;
  end process;
end architecture;

Concurrent statements (assignments, instances, generate, processes) sit in the architecture body and run concurrently. Sequential statements (if, case, loop, wait, and assignments) sit inside a process or subprogram and run in order. You cannot put an if directly in the architecture body, nor a concurrent instance inside a process — each belongs to its world.

3. Production-quality RTL — the same logic, either world

A simple mux can be written concurrently or sequentially — same hardware, different world:

-- CONCURRENT: a conditional signal assignment in the architecture body
y_conc <= a when sel = '1' else b;
 
-- SEQUENTIAL: the equivalent inside a process
proc : process (a, b, sel)
begin
  if sel = '1' then y_seq <= a;
  else             y_seq <= b;
  end if;
end process;

What hardware does this become? Both are the same 2:1 multiplexer. The concurrent form is terse; the sequential form (a process) scales better to multi-step behaviour, clocked logic, and complex control. Choosing between them is choosing a description style, not a different circuit — the synthesised gate is identical.

4. Hardware interpretation — both describe hardware

5. Simulation interpretation — concurrent always-on, sequential run-to-suspend

In simulation the distinction is concrete. Concurrent statements are all live, each re-evaluated by the event-driven engine when its inputs change (Module 4). A process, though concurrent as a whole, runs its sequential body to completion in zero time when triggered, then suspends — and its signal assignments take effect one delta later (Module 3). So "sequential" means ordered execution within one wake-up, not stepping across simulation time.

6. Debugging example — a sequential statement in the wrong world

Expected: an if used to choose a value compiles. Observed: a compile error — a sequential statement placed directly in the architecture body. Root cause: if, case, and loops are sequential statements; they are illegal in the concurrent architecture body and belong inside a process. The concurrent equivalent is a conditional (when/else) or selected (with/select) assignment. Fix: either wrap the logic in a process or use the concurrent assignment form. Engineering takeaway: the compiler is telling you which world you are in — if a statement is rejected in the architecture body, it is sequential and needs a process (or its concurrent counterpart).

-- WRONG: 'if' (sequential) directly in the architecture body → compile error.
-- if sel = '1' then y <= a; else y <= b; end if;
-- FIX A: use the concurrent conditional assignment (stay in the concurrent world).
y <= a when sel = '1' else b;
-- FIX B: wrap it in a process (enter the sequential world).
process (a, b, sel) begin
  if sel = '1' then y <= a; else y <= b; end if;
end process;

7. Common mistakes & what to watch for

• Putting if/case/loops in the architecture body. They are sequential; use a process or the concurrent when/else / with/select forms.
• Putting concurrent statements inside a process. Instances, generate, and concurrent assignments belong in the architecture body, not inside a process.
• Thinking sequential means "happens over time." Within one wake-up the body runs in zero time; signal updates still follow the delta model.
• Assuming the two forms differ in hardware. A mux written concurrently or in a process is the same circuit; the choice is description style.
• Forgetting a process is one concurrent statement. Multiple processes run in parallel with each other and with concurrent assignments.

8. Engineering insight

The concurrent/sequential split is the organising principle of VHDL: the architecture is a parallel netlist, and processes are the pockets of ordered, behavioural description inside it. Mastering the boundary tells you instantly where any statement belongs and which mental model to apply — parallel-and-order-free for the body, ordered-within-a-wake-up for a process. The process is the hinge between the two, and because almost all real behaviour (clocked registers, FSMs, complex combinational logic) is written in processes, the rest of the language now pivots to them.

9. Summary

Concurrent statements live in the architecture body and run in parallel (order irrelevant); sequential statements live inside a process (or subprogram) and execute top to bottom. A process is a single concurrent statement whose interior is sequential — the bridge between the worlds. Both describe hardware; sequential ordering is execution order within one wake-up, not elapsed time, and the same logic can often be written either way for the identical circuit.

10. Learning continuity

With the boundary clear, the next module enters the sequential world in full. The Process Statement introduces the process construct itself — its two trigger styles (sensitivity list and wait), how its body executes and suspends, and how it becomes combinational or registered hardware — the foundation for if/case/loops, variables, and every clocked design that follows.