The Process Statement

1. Engineering intuition — a recipe that runs on a trigger

A process is a little engine that sits idle until something it cares about happens, then runs a recipe top to bottom and goes back to sleep. That recipe describes behaviour — "on a clock edge, capture the input"; "whenever any input changes, recompute the output." The whole thing is one parallel block in the architecture, but inside it you finally get ordered, step-by-step code, which is what complex logic (registers, state machines, multi-step decisions) needs.

2. Formal explanation — structure and the two trigger styles

-- (1) SENSITIVITY-LIST style: re-runs whenever a listed signal changes.
proc1 : process (a, b)
begin
  y <= a and b;            -- sequential body
end process;
 
-- (2) WAIT style: suspends explicitly at wait statements (no sensitivity list).
proc2 : process
begin
  wait until rising_edge(clk);   -- suspend here until the edge
  q <= d;
end process;

A process has an optional label, an optional sensitivity list, a declarative region (where variables live, lesson 3.1), and a sequential body between begin and end process. It is triggered either by a sensitivity list or by wait statements — never both (a process with a sensitivity list may not contain wait). The body's statements are sequential; the process as a whole is one concurrent statement among many.

3. Production-quality RTL — combinational and clocked processes

The same construct expresses both kinds of logic, distinguished by style:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
-- COMBINATIONAL process: sensitive to all inputs, no clock → pure logic.
comb : process (a, b)
begin
  sum <= std_logic_vector(unsigned(a) + unsigned(b));
end process;
 
-- CLOCKED process: sensitive to clk, guarded by rising_edge → a register.
reg : process (clk)
begin
  if rising_edge(clk) then
    q <= sum;                  -- captured on the edge → flip-flops
  end if;
end process;

What hardware does this become? comb is an adder (combinational logic); reg is a register that captures sum on each rising clock edge. The difference is entirely in the body's style — a clock-edge guard makes it sequential (registered) logic; its absence makes it combinational.

4. Hardware interpretation — process style decides comb vs registered

5. Simulation interpretation — wake, run, suspend

The process execution model is the heart of this lesson. A process is suspended until its trigger fires; then it runs its entire body in zero simulated time — variables update immediately, signal assignments are scheduled — reaches end process (or a wait), and suspends again. The scheduled signals update one delta later and wake any readers.

6. Debugging example — the process that never suspends

Expected: a process runs when triggered. Observed: the simulator hangs at time zero, or makes no progress, pinning the CPU. Root cause: the process has neither a sensitivity list nor a wait — so nothing ever suspends it; it runs its body, loops to the top, and runs again forever in zero time. Fix: give it a trigger — a sensitivity list for combinational logic, or a wait/clock-edge guard for sequential logic. Engineering takeaway: every process must have a way to suspend; a process with no sensitivity list and no wait is an infinite zero-time loop, the classic cause of a hung simulation.

-- WRONG: no sensitivity list, no wait → runs forever, sim hangs.
process
begin
  y <= a and b;          -- nothing suspends the process; it re-runs endlessly
end process;
-- RIGHT: add a trigger so it suspends after each run.
process (a, b)           -- sensitivity list → re-run only when a or b changes
begin
  y <= a and b;
end process;

7. Common mistakes & what to watch for

• No trigger at all. A process with neither a sensitivity list nor a wait loops forever; add one. (A deliberate testbench wait; at the end also works to stop it once.)
• Mixing a sensitivity list with wait. Illegal — a process uses one style or the other.
• Expecting signal assignments to take effect mid-body. They are scheduled and update after the process suspends; use variables for immediate intermediate values (lesson 3.1).
• Forgetting the clock-edge guard for registers. Without rising_edge(clk), a clocked-looking process may infer latches or combinational logic instead of flip-flops.
• Treating a process as sequential across time. Its body runs in zero time per wake-up; time passes only at wait/between triggers.

8. Engineering insight

The process is the workhorse of behavioural VHDL, and its power comes from one disciplined model: triggered → run body to completion → suspend → delta-update signals. That single loop underlies both combinational logic (a complete sensitivity list, no clock) and every register and state machine (a clock-edge guard). Internalise "a process must be able to suspend" and "signals update after suspend," and processes stop being mysterious: they are ordered recipes that the engine runs on triggers and that synthesis turns into gates or flip-flops depending on how you guard them.

9. Summary

A process is one concurrent statement whose body is sequential, triggered by either a sensitivity list or wait statements (never both). When triggered it runs its body in zero time — variables immediate, signals scheduled — then suspends, and the scheduled signals update one delta later. A clock-edge guard makes it registered logic; its absence makes it combinational. A process with no trigger loops forever and hangs the simulation.

10. Learning continuity

A sensitivity-list process re-runs when a listed signal changes — which raises the obvious question of which signals to list. The next lesson, The Sensitivity List, covers exactly that: why a combinational process must list every signal it reads (or risk a simulation-versus-synthesis mismatch), why a clocked process lists only the clock and async reset, and how VHDL-2008's process(all) removes the guesswork.