Bus Ownership Handover

This closes Module 10 by assembling the full bus ownership handover — the complete, cycle-by-cycle transfer of the bus from one master to another, synthesizing the grant handshake (10.2) and the arbitration timing (10.8). The sequence: master A owns the bus; the arbiter grants B; A finishes its last transfer while B waits; at the transfer boundary, with HGRANT for B and HREADY high, B takes over — driving its first address phase, which overlaps A's last data phase (the pipeline); then B fully owns the bus. The handover is clean (ownership changes only between transactions, gated on HREADY high, so no two masters drive at once) and efficient (the pipeline overlap wastes no cycle — the bus stays busy across the change). The interconnect switches the bus driver to B at exactly the handover cycle. This clean, glitch-free, efficient ownership change is the foundation of correct multi-master operation — the culmination of the arbitration mechanism.

1. What Is It?

A bus ownership handover is the complete transfer of the bus from one master to another. The sequence (A → B):

1. A owns the bus (A drives it).
2. The arbiter grants B (HGRANT to B); B waits.
3. A completes its last transfer (HREADY high at the boundary).
4. B takes over — drives its first address phase (overlapping A's last data phase).
5. B fully owns the bus.

So the handover is the orchestrated transition from A's ownership to B's. It combines everything from this module: the grant (10.2, HGRANT to B), the timing (10.8, B drives at HGRANT + HREADY high), and the pipeline overlap (10.8, B's address overlaps A's data). The result is a clean handover (no collision — B waits for A's transfer to complete) that's also efficient (no idle cycle — the pipeline overlap keeps the bus busy). The interconnect switches the bus's driver from A to B at the handover cycle. So a bus ownership handover is the complete, clean, efficient transfer of the bus between masters — the mechanism by which the multi-master bus is shared over time.

2. Why Does It Exist?

The handover mechanism exists because the multi-master bus must be shared over time — passed from master to master — and that passing must be clean (no collision, no corruption) and efficient (no wasted cycles), which requires the orchestrated sequence.

The bus is shared (chapter 10.1): only one master owns it at a time, so over time it must pass between masters as their needs change. This passing is the handover. It must be clean: if the passing caused two masters to drive at once (a collision) or interrupted a transfer mid-way, the bus would be corrupted. So the handover exists to transfer ownership safely — A relinquishes, B takes over, with no overlap-collision and no interrupted transfer. The orchestrated sequence (grant, wait for completion, take over) is what makes this safe. So the handover exists as the safe ownership-transfer mechanism — the bus changes hands cleanly.

The reason the handover is gated on A's transfer completing (HREADY high) is the clean-handover requirement (chapter 10.8): B must wait for A's last transfer to finish before driving, or B and A would collide. So the handover sequence includes B waiting for A's completion (step 3) — this is what makes it clean. So the handover exists with this gating to ensure A's transfer completes before B drives — the no-collision guarantee. The sequence isn't just "grant B and switch"; it's "grant B, wait for A to finish, then switch" — the waiting is essential.

The reason the handover is pipelined (B's address overlaps A's data) is efficiency (chapter 10.8): a non-pipelined handover (B starts only after A fully finishes, including A's data phase) would waste a cycle (the bus idle between A's last transfer and B's first). The pipeline overlap avoids this: B's first address phase happens during A's last data phase, so B starts immediately, no idle cycle. So the handover is pipelined to keep the bus efficient — no wasted cycles across the ownership change. So the handover exists in this pipelined form to be both clean (gated on completion) and efficient (overlapped) — transferring ownership safely without losing throughput. The whole sequence is designed to achieve both: the gating for cleanness, the overlap for efficiency.

3. Mental Model

Model the bus handover as a smooth shift change at a single workstation — the incoming worker steps in and starts the next task exactly as the outgoing worker finishes their current one, so the station never sits idle and they never both grab the same tool.

A single workstation (the bus) is operated by one worker at a time (one master). At a shift change (handover), the outgoing worker (master A) finishes their current task (last transfer), and the incoming worker (master B) steps in. The change is choreographed: B is told they're next (granted), B waits for A to finish the current task (waits for HREADY high — A's transfer completing), and then B starts the next task exactly as A wraps up — so the station never sits idle (no wasted cycle) and they never both grab the same tool (no collision). For a moment in the changeover, A is finishing up (completing the data of the last task) while B is already starting (beginning the next task's setup) — but they're doing different things (A finishing, B starting), so no conflict. Then A leaves and B has the station. The shift change is smooth: no idle time, no collision.

This captures the handover: the single workstation = the bus; the shift change = the ownership handover; B told they're next = HGRANT to B; B waiting for A to finish = waiting for HREADY high; B starting as A wraps up = B's address overlapping A's data (the pipeline); never both grabbing the same tool = no collision (different buses); no idle station = no wasted cycle. A smooth, choreographed shift change.

Watch the full handover cycle by cycle:

The model's lesson: a smooth shift change — B steps in as A finishes, no idle, no collision. In the waveform, HMASTER switches A→B at the boundary, B's first address overlaps A's last data, and B takes over with no wasted cycle. The handover is choreographed: grant, wait for completion, overlap, take over.

4. Real Hardware Perspective

In hardware, the handover is implemented by the arbiter (granting B, switching HMASTER) and the interconnect (muxing the bus's address-phase signals from A to B at the handover cycle), with B's drive-gating on HGRANT + HREADY high producing the clean, pipelined transition.

The arbiter's role in the handover: it grants B (HGRANT to B, deasserting A's), and it switches HMASTER from A to B at the handover (chapter 10.3). So the arbiter signals the ownership change — the grant tells B it's next, and HMASTER tells the fabric the new owner. The arbiter's grant decision (per its policy, chapters 10.5–10.6) initiated the handover; the grant/HMASTER signals carry it out.

The interconnect's role: it muxes the bus's address-phase signals (HADDR, HTRANS, HSIZE, HWRITE, HBURST) from A's outputs to B's at the handover cycle (chapter 3.11). So when B takes the bus, the interconnect switches the bus's address-phase drivers to B's outputs — the physical ownership transfer. The data-phase signals follow one cycle later (the pipeline). So the interconnect implements the actual driver switch, timed to the handover. So in hardware, the arbiter decides and signals the handover, and the interconnect executes the driver switch.

The B's drive-gating completes it: B drives its first address phase when it samples HGRANT and HREADY high (chapter 10.8), which is when the interconnect switches the driver to B. So B and the interconnect are coordinated: B drives at the right cycle, the interconnect muxes to B at that cycle. The result is the clean, pipelined handover — B's address overlapping A's data, no collision (different buses), no idle cycle. So the hardware handover is the coordinated action of the arbiter (grant/HMASTER), the interconnect (driver mux), and B (drive-gating) — all timed to the HGRANT + HREADY-high boundary.

A hardware note on the interconnect / bus-matrix context (chapter 12.x): in a single shared bus, the handover switches the whole bus from A to B. In a bus matrix (separate paths per master), masters don't share one bus, so the "handover" applies per-subordinate-port — when masters' paths converge on one subordinate, the per-port arbitration hands the subordinate's access between masters with the same clean, pipelined timing. So the handover mechanism applies whether on a single shared bus (whole-bus handover) or in a matrix (per-port handover). The principles (grant, wait for completion, pipelined overlap) are the same. So in hardware, the handover is implemented in the arbiter+interconnect, applied at the appropriate granularity (whole bus or per-port).

5. System Architecture Perspective

At the system level, the bus ownership handover is the mechanism by which the multi-master bus is shared over time — and its cleanness and efficiency are the foundation of correct, performant multi-master operation, realized in the interconnect.

The time-sharing foundation is the handover's role: a multi-master bus is shared by time-multiplexing — different masters own it at different times, passing it via handovers. So the handover is how the time-sharing happens — each ownership change is a handover. So the bus's multi-master operation is a sequence of handovers, interleaving the masters' transfers over time. So the handover is the fundamental operation of multi-master bus sharing — the bus's whole multi-master behavior is built from handovers. Getting the handover right (clean, efficient) is therefore essential to the multi-master system working at all.

The cleanness as correctness is the key system property: because each handover is clean (no collision, no interrupted transfer, gated on completion), the multi-master bus operates correctly — masters share it without corrupting each other's transfers. So the handover's cleanness is the correctness foundation of multi-master operation. A flawed handover (collision, or interrupting a transfer) would corrupt the bus — so the clean handover is what makes multi-master AHB reliable. So at the system level, the clean handover is a correctness requirement, the basis of safe bus sharing.

The efficiency as performance is the complementary property: because each handover is efficient (pipelined overlap, no idle cycle), the multi-master bus maintains its throughput across handovers — no cycles wasted at ownership changes. So the handover's efficiency preserves the bus's performance even as ownership changes frequently. In a busy multi-master system with many handovers, this efficiency matters — wasted cycles per handover would accumulate. So the pipelined handover keeps multi-master throughput high. So at the system level, the handover is both the correctness foundation (clean) and a performance contributor (efficient) of multi-master operation — and it's realized in the interconnect's arbiter+muxing design. A well-designed multi-master interconnect implements clean, efficient handovers, enabling correct and performant bus sharing. So the bus ownership handover is the capstone of the multi-master module: it's the complete mechanism that ties together arbitration (who gets the bus), timing (when), and the pipeline (efficient transfer) into the clean, efficient ownership change that makes multi-master AHB work. (Modern bus-matrix interconnects apply this per-port, sharing each subordinate among masters via clean handovers.)

6. Engineering Tradeoffs

The bus handover embodies the clean-and-efficient ownership-transfer design.

• Clean handover (gated) vs fast-but-risky. Gating the handover on the current transfer's completion (HREADY high) ensures cleanness (no collision) at the cost of B waiting for A to finish. A faster handover (B drives immediately) would risk collision. The gated handover is the safe choice.
• Pipelined overlap (efficient) vs full-stop. Overlapping B's address with A's data keeps the bus busy (no idle cycle) at the cost of the one-cycle overlap (two masters active on different buses). A full-stop handover would waste a cycle. The overlap is more efficient.
• Between-transaction handover vs preemption. Changing ownership only between transactions ensures transfers complete cleanly at the cost that a master holds the bus for its whole transaction (a long burst delays the handover). Preemption mid-transaction would be complex/unsafe. AHB hands over between transactions.
• Interconnect-implemented vs ad-hoc. Implementing the handover in the interconnect (arbiter + muxing) gives a clean, standard mechanism at the cost of the interconnect logic. An ad-hoc scheme would be error-prone. The interconnect approach is standard.

The throughline: a bus ownership handover transfers the bus from one master to another — A owns, B is granted, A completes, B takes over (at HGRANT + HREADY high, overlapping A's last data), B owns — a clean (gated on completion, no collision) and efficient (pipelined overlap, no idle cycle) ownership change. It's the mechanism by which the multi-master bus is time-shared, implemented in the interconnect (arbiter + driver muxing). The clean handover is the correctness foundation of multi-master operation; the efficient overlap preserves throughput. The handover is the capstone synthesizing arbitration, timing, and the pipeline.

7. Industry Example

Trace a complete bus handover in a multi-master system.

A system hands the bus from a CPU (master A) to a DMA engine (master B).

• The CPU owns the bus. The CPU (A) is executing, driving transfers on the bus. It owns the bus (HMASTER = A).
• The DMA is granted. The DMA (B) needs the bus (it has data to move), so it requests (HBUSREQ_B). The arbiter, per its policy, grants the DMA (HGRANT → B, deasserting the CPU's grant). So B is now "next."
• The CPU finishes its current transfer. B waits while the CPU completes its current transfer. The transfer finishes — HREADY high at the boundary. Now B has HGRANT and HREADY both high.
• The DMA takes over. On the next cycle, the arbiter switches HMASTER to B, the interconnect muxes the bus's address-phase signals to the DMA's outputs, and the DMA drives its first address phase. Crucially, this first address phase overlaps the CPU's last data phase (the pipeline) — the address bus carries the DMA's transfer, the data bus the CPU's last data. No collision (different buses), no idle cycle.
• The DMA owns the bus. After the overlap cycle, the bus is fully the DMA's — it drives its address and data phases, streaming its transfer. The handover is complete: the bus passed cleanly and efficiently from the CPU to the DMA.
• Later handover back. When the DMA finishes (or the arbiter switches per its policy), the bus hands back to the CPU (or another master) with the same clean, pipelined sequence. So the bus is continuously time-shared via these handovers — CPU, DMA, CPU, etc. — each clean and efficient.

The example shows the complete handover: the CPU owns the bus, the DMA is granted, the CPU finishes (HREADY high), the DMA takes over (HMASTER switches, interconnect muxes, DMA's address overlaps the CPU's last data), and the DMA owns the bus — clean (no collision, gated on completion) and efficient (no idle cycle, pipelined overlap). The bus is time-shared via these handovers, each orchestrated by the arbiter and interconnect. This is how multi-master AHB shares the bus over time.

8. Common Mistakes

9. Interview Insight

The bus ownership handover is a synthesizing interview topic — the full sequence, the cleanness (gated/between-transactions), and the efficiency (pipelined overlap) are the signals.

The answer that lands gives the sequence and both properties: "The bus ownership handover transfers the bus from one master to another. The sequence: master A owns the bus; the arbiter grants master B; A finishes its last transfer while B waits; at the transfer boundary, when B has HGRANT and HREADY both high — meaning B is granted and A's transfer is completing — B takes over, driving its first address phase; and then B fully owns the bus. It's clean for two reasons: ownership changes only between transactions, not mid-transfer, so transfers complete cleanly; and the new master waits for HREADY high, so A's transfer finishes before B drives — no two masters driving at once, no collision. It's efficient because it's pipelined: B's first address phase overlaps A's last data phase — the address bus carries B, the data bus carries A's completion, on different buses — so there's no idle cycle, the bus stays busy across the handover. In hardware, the arbiter grants B and switches HMASTER, and the interconnect muxes the bus's address-phase signals from A to B at the handover cycle. So it's a glitch-free, efficient ownership change — the mechanism by which the multi-master bus is time-shared." The full sequence, the cleanness (between transactions, gated on HREADY high), and the efficiency (pipelined overlap) are the senior signals.

10. Practice Challenge

Reason from the bus handover.

1. State the sequence. Give the steps of a bus ownership handover from A to B.
2. Cleanness. Explain the two things that make the handover clean (no collision).
3. Read the waveform. From Figure 2, identify where HMASTER switches and where B's address overlaps A's data.
4. Efficiency. Explain why the pipelined handover wastes no cycle.
5. Roles. Explain the arbiter's and interconnect's roles in the handover.

11. Key Takeaways

• A bus ownership handover transfers the bus from one master to another: A owns → arbiter grants B → A finishes (B waits) → at HGRANT(B) + HREADY high, B drives its first address (overlapping A's last data) → B owns.
• It's clean — ownership changes only between transactions and the new master is gated on HREADY high (waits for the old transfer to complete), so no two masters drive at once (no collision).
• It's efficient — the handover is pipelined: the new master's first address phase overlaps the old master's last data phase (different buses, no collision), so there's no idle cycle (the bus stays busy).
• The arbiter grants B and switches HMASTER; the interconnect muxes the bus driver from A to B at the handover cycle; B gates its drive on HGRANT + HREADY high — all coordinated.
• The handover is how the multi-master bus is time-shared — the bus's whole multi-master operation is a sequence of handovers.
• Cleanness is the correctness foundation; efficiency preserves throughput — both achieved by the same orchestrated sequence (HREADY-gating + pipeline overlap). The handover is the capstone synthesizing arbitration, timing, and the pipeline.

12. What Comes Next

This completes Module 10 — Arbitration & Multi-Master AHB. You now understand why arbitration exists, the request/grant handshake (HBUSREQ/HGRANT), HMASTER, locked transfers (HLOCK), the policies (fixed-priority, round-robin), starvation, the arbitration timing, and the bus ownership handover. The next module turns to how the address is decoded to select subordinates:

• Module 11 — Decoder & Slave Selection (coming next) — the address decoder, HSEL generation, address maps, and default slaves.

To revisit the arbitration timing this builds on, see Arbitration Timing; for the grant handshake, HBUSREQ & HGRANT. For the interconnect that implements the handover, see Master, Slave, Decoder & Arbiter. For the broader protocol map, see the AMBA family overview.