Arbitration Timing

Chapter 10.2 introduced the grant-then-own principle (a grant means "you're next"); this chapter gives the precise cycle-by-cycle timing. The arbiter asserts HGRANT, and the granted master takes the bus on the cycle after it samples HGRANT together with HREADY high — the combination meaning it's granted AND the current transfer is completing (the bus is free). The master then drives its address phase and becomes the owner. The HREADY condition is what ensures the previous master's transfer finishes first, so the handover is clean (no two masters driving at once). And because AHB is pipelined, at the handover cycle the new master's first address phase overlaps the old master's last data phase — the address bus carries the new transfer while the data bus carries the old one's completion. So arbitration timing is: drive on the cycle after HGRANT + HREADY high, with a clean one-phase overlap of the two masters.

1. What Is It?

Arbitration timing is the precise timing of when a granted master takes the bus: the master drives its address phase on the cycle after it samples HGRANT and HREADY both high.

So the timing condition is HGRANT and HREADY both high: HGRANT means "you're granted," HREADY high means "the current transfer is completing" (the bus is becoming free). When the granted master samples both high (at a transfer boundary), it knows the bus is its to drive — so on the next cycle, it drives its address phase. The HREADY part is crucial: it makes the master wait for the current transfer to finish. If HREADY is low (the current transfer is in a wait state), the master waits — it doesn't take the bus until the current transfer completes (HREADY goes high). So the granted master takes the bus exactly when the bus is free (current transfer done) and it's granted — a clean, defined handover.

2. Why Does It Exist?

This timing exists to make the handover clean — ensuring the previous master's transfer completes before the new master drives, so there's never two masters driving the bus at once.

The danger to avoid is two masters driving simultaneously (a collision, chapter 10.1). When the arbiter grants a new master, the previous master may still be completing its transfer (its data phase, possibly with wait states). If the new master drove immediately on the grant, it could collide with the previous master still driving. So the new master must wait for the previous transfer to complete. The HREADY high condition provides exactly this: HREADY high marks the current transfer completing, so the new master takes the bus only then — after the previous transfer finishes. So the timing exists to gate the handover on the current transfer's completion (HREADY high), preventing the collision. The "drive after HGRANT + HREADY high" rule is the clean-handover guarantee.

The reason it's the cycle after (not the same cycle) is the pipeline (chapter 5.2): the new master drives its address phase in the cycle after the handover condition, and its data phase the cycle after that — following the standard address-then-data pipeline. So the new master's transfer begins (address phase) on the cycle after HGRANT + HREADY high, which is the natural pipeline timing: the address phase is the first phase of its transfer. So "the cycle after" places the new master's address phase right after the bus becomes free — the earliest clean point for it to start. This is the standard pipeline cadence applied to the handover.

The reason the new master's first address phase overlaps the old master's last data phase is the pipeline overlap (chapter 5.2):

In the AHB pipeline, an address phase always overlaps the previous transfer's data phase. At the handover, the previous transfer is the old master's last one — so the new master's first address phase overlaps the old master's last data phase. So for one cycle, the address bus carries the new master (B), and the data bus carries the old master (A). This is just the normal address-leads-data pipeline (chapter 5.2), spanning the two masters at the handover. So the overlap exists because the pipeline always overlaps consecutive transfers' phases — and at the handover, those consecutive transfers belong to different masters. After that one overlap cycle, the bus is fully the new master's. So the timing produces a clean, pipelined handover with a one-phase overlap — no collision (different buses: address for B, data for A), and the pipeline cadence maintained.

3. Mental Model

Model arbitration timing as a relay race baton pass — the incoming runner starts running (drives the address) as the outgoing runner finishes their leg (completes the data phase), so for a moment both are in motion in the exchange zone, but they're doing different things (one handing off, one taking off).

In a relay (the pipelined bus), the baton (bus ownership) passes from the outgoing runner (old master) to the incoming runner (new master). The incoming runner doesn't start after the outgoing runner fully stops — that would lose time. Instead, in the exchange zone, the incoming runner starts running (drives the address phase) as the outgoing runner finishes their leg (completes the last data phase). So for a moment, both are moving — but they're doing different things: the outgoing runner is completing their stride (finishing the data), the incoming runner is taking off (starting the address). They don't collide because they're at different points (different buses). The handoff is gated on the outgoing runner reaching the exchange zone (HREADY high — the current transfer completing) — the incoming runner takes off then, not before (or they'd collide).

This captures the timing: the baton pass = the ownership handover; the incoming runner starting as the outgoing finishes = the new master's address overlapping the old master's data; gated on reaching the exchange zone = drive after HGRANT + HREADY high (current transfer completing); both moving but doing different things = the address bus (new) and data bus (old) carrying different masters, no collision. The overlap is efficient (no lost time) and clean (different buses).

Watch the precise grant-to-drive timing:

The model's lesson: the incoming master takes off (drives the address) exactly as the outgoing one finishes (HREADY high), gated on the current transfer completing. In the waveform, B is granted but waits while A's transfer is in a wait state (HREADY low); when HREADY goes high (A completing), B drives next cycle. The handover is gated on the current transfer's completion — clean and pipelined.

4. Real Hardware Perspective

In hardware, the granted master's control logic gates its address-phase driving on (HGRANT and HREADY high), and the handover produces the pipeline overlap naturally — the new master's address-phase registers feed its data phase the next cycle, while the old master's last data completes.

The master's drive-gating logic is the key: the granted master begins driving its address phase only when it has sampled HGRANT and HREADY both high. So its control logic is: if (HGRANT and HREADY high), start the address phase next cycle. While HGRANT is high but HREADY is low (the current transfer in a wait state), the master waits — it doesn't drive. So the master's bus-driving is gated on this combined condition (chapter 10.2's grant-then-own, now precise). This gating is what makes the master take the bus at exactly the right (clean) moment.

The pipeline overlap happens automatically from the pipelined drive: when the new master drives its first address phase (at the handover), the old master's last data phase is still in progress (it was issued the previous cycle). So the address bus has the new master's transfer, the data bus the old master's — the natural pipeline overlap (chapter 5.2). There's no special handover logic for this; it's just the pipeline cadence applied across the two masters. The new master's address-phase outputs drive the bus, and the old master's data-phase logic completes its last transfer — on different buses, so no conflict. So in hardware, the handover overlap is the pipeline working normally, just spanning two masters.

The wait-state handling is a hardware detail: if the current (old master's) transfer is in a wait state (HREADY low), the new master waits (it has HGRANT but not HREADY high). So a wait state delays the handover — the new master takes the bus only when the current transfer finally completes (HREADY high). So in hardware, the handover timing accounts for wait states: the new master's drive-gating on HREADY high means it waits out any wait states of the current transfer. This is correct — the current transfer must fully complete (including its wait states) before handover. So the timing naturally handles wait states by gating on HREADY high.

A hardware note on the address-phase signals at handover: when the new master drives its first address phase, all its address-phase outputs (HADDR, HTRANS, HSIZE, HWRITE, HBURST) become the new master's — driven onto the (now shared-ownership) bus. The interconnect/multiplexing (chapter 3.11) switches the bus's address-phase signals to the new master's outputs at the handover (controlled by the grant/HMASTER). So in hardware, the handover involves the interconnect muxing the address-phase signals from the old master's outputs to the new master's, at the right cycle (when the new master takes the bus). So the handover is the interconnect switching the bus's driver to the new master, timed by the grant + HREADY-high condition. This muxing is part of the multi-master interconnect (chapter 3.11, 12.x).

5. System Architecture Perspective

At the system level, the arbitration timing ensures glitch-free bus handover — the foundation of correct multi-master operation — and its overlap (pipelined handover) keeps the bus efficient (no idle cycles between masters).

The glitch-free handover is the core system guarantee: because the new master takes the bus only when the current transfer completes (HGRANT + HREADY high), there's never a moment when two masters drive the bus simultaneously — the handover is clean. So the arbitration timing is what makes multi-master operation correct: masters hand over the bus without collisions. This is essential — a collision would corrupt the bus. So the timing's clean-handover guarantee is the foundation of reliable multi-master AHB. Every ownership change is glitch-free because of this timing.

The efficiency of the pipelined handover is a system benefit: because the new master's first address phase overlaps the old master's last data phase (rather than waiting for the old transfer to fully finish before starting), there's no idle cycle between the two masters' transfers — the bus stays busy across the handover. So the handover is not only clean but efficient: the pipeline overlap means the new master starts as soon as possible, with no wasted cycle. So the arbitration timing maintains the bus's pipelined throughput even across master handovers — no bubble inserted at the ownership change. This efficiency matters for multi-master throughput: handovers don't waste cycles.

The interconnect's role is where this timing is implemented at the system level (chapters 3.11, 12.x): the interconnect contains the arbiter and the address-phase muxing that switches the bus driver between masters at the handover. So the arbitration timing is realized in the interconnect's design — the arbiter's grant logic plus the muxing, coordinated to produce the clean, pipelined handover. So a correct multi-master interconnect must implement this timing precisely: grant per the policy, switch the driver at HGRANT + HREADY high, maintain the pipeline overlap. So at the system level, the arbitration timing is a key interconnect-design requirement — getting it right ensures glitch-free, efficient multi-master operation. (In modern bus-matrix interconnects, the handover timing applies per-subordinate-port where masters' paths converge.) So the arbitration timing is the precise mechanism behind clean, efficient multi-master bus sharing — the foundation that the whole multi-master module rests on.

6. Engineering Tradeoffs

The arbitration timing embodies the clean-pipelined-handover design.

• Gate on HREADY (clean) vs grant-immediately (risky). Gating the new master's drive on HREADY high ensures the current transfer completes first (clean handover, no collision) at the cost of the new master waiting out the current transfer (including its wait states). Granting-immediately would risk collisions. The HREADY gate is the safe choice.
• Pipelined overlap (efficient) vs full-stop handover. Overlapping the new master's address with the old master's data (the pipeline) keeps the bus busy (no idle cycle) at the cost of the one-cycle overlap (two masters active on different buses). A full-stop handover (old fully done before new starts) would waste a cycle. The overlap is more efficient.
• Wait-state-aware handover. Gating on HREADY high makes the handover wait out the current transfer's wait states — correct (the transfer must fully complete) at the cost of the new master waiting. This is necessary for correctness.
• Interconnect muxing vs simpler scheme. The interconnect muxing the bus driver between masters (timed precisely) enables clean handover at the cost of the muxing logic. This is the standard multi-master interconnect approach.

The throughline: the granted master drives its address phase on the cycle after HGRANT and HREADY are both high — ensuring the current transfer completes first (clean handover, no collision), with the new master's first address phase overlapping the old master's last data phase (the pipeline, keeping the bus efficient — no idle cycle). The HREADY condition gates the handover on the current transfer's completion (waiting out wait states), and the interconnect muxes the bus driver at the right cycle. This timing is the foundation of glitch-free, efficient multi-master bus sharing.

7. Industry Example

Trace the arbitration timing of a handover.

A system hands the bus from master A (a CPU) to master B (a DMA) — B has been granted.

• B is granted, A is finishing. The arbiter has asserted HGRANT to B (per its policy). Meanwhile, master A is completing its current transfer. B has HGRANT but must wait for A's transfer to complete.
• A's transfer has a wait state. A's current transfer hits a wait state (the slave drives HREADY low — it needs more time). So even though B is granted, HREADY is low — B waits (HGRANT high but not HREADY high). B doesn't take the bus yet, because A's transfer isn't done.
• A's transfer completes. The slave finishes A's transfer, driving HREADY high. Now B has HGRANT and HREADY both high — the bus is free and B is granted. So on the next cycle, B drives its address phase, becoming the owner.
• The pipelined handover. At that handover cycle, B's first address phase is on the address bus, while A's last data phase is still completing on the data bus (the pipeline overlap). So for one cycle, the address bus carries B's transfer and the data bus carries A's completion — different buses, no collision. After that, the bus is fully B's.
• No idle cycle. Because of the pipeline overlap, there's no idle cycle between A's last transfer and B's first — B starts as soon as A's last transfer completes. So the handover is efficient: the bus stays busy across the ownership change. The interconnect muxed the address-phase signals from A's outputs to B's at the right cycle.
• A collision avoided. Had B driven the bus the moment it was granted (ignoring HREADY) — during A's wait state — B and A would have collided (both driving). The HREADY gate prevented this: B waited until A's transfer completed. So the timing ensured a clean handover.

The example shows the arbitration timing: B (granted) waits while A's transfer is in a wait state (HREADY low), takes the bus when A completes (HREADY high), and drives its address phase the next cycle — with B's first address overlapping A's last data (the pipeline), no idle cycle, no collision. The HREADY gate ensured the clean handover; the pipeline overlap kept it efficient.

8. Common Mistakes

9. Interview Insight

Arbitration timing is a precise interview topic — the HGRANT-plus-HREADY-high condition and the pipelined-handover overlap are the signals.

The answer that lands gives the condition and the overlap: "The granted master takes the bus on the cycle after it samples HGRANT and HREADY both high. HGRANT means it's granted; HREADY high means the current transfer is completing, so the bus is free. Together, at a transfer boundary, they mean the bus is the master's to drive — so on the next cycle, it drives its address phase. The HREADY condition is crucial: it makes the master wait for the current transfer to finish, including any wait states — so the previous master's transfer completes before the new one drives, ensuring a clean handover with no collision. If HREADY is low — the current transfer is in a wait state — the granted master waits. And because AHB is pipelined, at the handover cycle the new master's first address phase overlaps the old master's last data phase: the address bus carries the new transfer, the data bus carries the old one's completion — different buses, so no collision, and no idle cycle (the bus stays busy across the handover). So the timing gives a clean, efficient, pipelined handover." The HGRANT-plus-HREADY-high condition, the clean-handover rationale, and the pipelined overlap are the senior signals.

10. Practice Challenge

Reason from the arbitration timing.

1. State the condition. Give the precise condition for when a granted master takes the bus.
2. Why HREADY. Explain why the master waits for HREADY high, not just HGRANT.
3. Read the waveform. From Figure 3, explain why B waits and when it drives.
4. The overlap. Explain how the new master's address overlaps the old master's data at handover.
5. Wait states. Explain how a wait state in the current transfer affects the handover timing.

11. Key Takeaways

• The granted master drives its address phase on the cycle after it samples HGRANT and HREADY both high — granted and the current transfer completing (bus free).
• The HREADY condition ensures the current transfer finishes first — the master waits out the current transfer (including wait states), so the handover is clean (no collision).
• Gating on HGRANT alone would cause a collision during the current transfer — the master must gate on HGRANT and HREADY high.
• The handover is pipelined — the new master's first address phase overlaps the old master's last data phase (address bus = new master, data bus = old master, different buses, no collision).
• No idle cycle at handover — the pipeline overlap keeps the bus busy across the ownership change (efficient).
• The interconnect muxes the bus driver from the old master to the new at the handover, timed by the grant + HREADY-high condition — the mechanism behind clean, efficient multi-master sharing.

12. What Comes Next

You now understand the arbitration timing. The final chapter of the module details the full handover:

• 10.9 — Bus Ownership Handover (coming next) — the complete clean handover of the bus between two masters, cycle by cycle.

To revisit the grant handshake this times, see HBUSREQ & HGRANT. For the pipeline the overlap follows, see The Two-Phase Pipeline and Address Phase Leads Data Phase. For the HREADY the timing gates on, see What HREADY Means. For the broader protocol map, see the AMBA family overview.