BUSY Cycles Inside Bursts

Chapter 8.10 covered how a burst ends. This chapter covers how a burst pauses without ending — via HTRANS=BUSY. When a master is in the middle of a burst but not ready with the next beat (e.g., its source FIFO momentarily emptied), it can drive BUSY to pause the burst — keeping the burst alive while taking a moment. During a BUSY cycle, no data transfers, the master holds the next beat's address, and the burst is not terminated — it resumes with a SEQ beat when the master is ready. The crucial distinction is that BUSY is master-side ("I, the master, am not ready") versus a wait state (HREADY low) which is slave-side ("I, the slave, need more time"). Both pause the bus, but from opposite sides — and BUSY lets a master pause mid-burst without losing the carefully-established burst sequence.

1. What Is It?

BUSY (an HTRANS value) is a master-inserted pause inside a burst: the master is still in the burst but not ready with the next beat. During a BUSY cycle:

• No data transfers — the BUSY cycle moves no data.
• The master holds the next beat's address — it presents the address of the beat it will issue when ready.
• The burst is not terminated — it stays alive and resumes with a SEQ beat when the master is ready.

So BUSY is the master's way of saying "hold on, I'm still in this burst but I need a moment." Unlike terminating the burst (changing HTRANS to IDLE or NONSEQ, chapter 8.10), BUSY keeps the burst going — it's a pause, not an end. The master inserts BUSY cycles between beats as needed, and the burst continues from where it paused. This lets a master that can't sustain back-to-back beats (because its data source is momentarily not ready) keep its burst alive rather than terminating and re-starting it — preserving the established sequence (the address pattern, the memory's prefetch).

2. Why Does It Exist?

BUSY exists because a master may not always be able to sustain back-to-back beats — its data source can momentarily stall — and without BUSY, such a master would have to terminate the burst (losing the established sequence) rather than just pause it.

Consider a master streaming a burst from a source that can momentarily run dry — a DMA reading from a FIFO that briefly empties, a master whose data isn't always ready every cycle. Without a pause mechanism, when the master can't provide the next beat, its only option would be to end the burst (drive IDLE) and restart it later — which loses the burst's benefits: the memory's prefetch is reset, the address sequence must be re-established (a new NONSEQ), and arbitration may be re-done. So terminating-and-restarting for a momentary stall is wasteful. BUSY exists to provide a pause instead: the master holds the burst alive through the stall and resumes, preserving the sequence and prefetch. So BUSY exists to let a master ride through momentary stalls without sacrificing the burst — a pause, not a restart.

The reason BUSY holds the next beat's address (rather than going idle) is to keep the burst positioned for resumption: by presenting the next beat's address during BUSY, the master keeps the burst's address pointer at the right place, so when it resumes (SEQ), it continues seamlessly from there. So holding the address is what makes the resumption clean — the burst is paused at the next beat, ready to go. If BUSY went fully idle (lost the address), resuming would be messier. So BUSY's address-holding keeps the burst poised to continue. This is why BUSY is a pause within the burst rather than a generic idle.

The reason BUSY is a distinct HTRANS value (separate from IDLE and SEQ) is to distinguish a pause from an end and from an active beat. SEQ means "here's the next beat" (active); IDLE means "no transfer, burst over" (end); BUSY means "no transfer, but burst continuing" (pause). So BUSY occupies a necessary middle ground: a non-transferring cycle that doesn't end the burst. Without a distinct BUSY, there'd be no way to express "pause without ending" — IDLE would end the burst, SEQ would force a beat the master can't provide. So BUSY exists as the HTRANS value for "in-burst pause," distinct from both active beats and burst termination. It completes the HTRANS vocabulary for bursts: NONSEQ (start), SEQ (continue), BUSY (pause), IDLE (end/none).

3. Mental Model

Model BUSY as pausing mid-sentence to gather your thoughts versus ending the conversation — "give me a second, I'm still talking" keeps the conversation going, whereas stopping and walking away ends it.

You're explaining something (streaming a burst). Sometimes you need a moment to find the next word (the next beat isn't ready). You have two options. You could stop and walk away (terminate the burst — drive IDLE), but then you'd have to come back and start the explanation over (a new NONSEQ, re-establishing context). Or you could say "give me a second... I'm still going" (drive BUSY) — pausing mid-sentence while keeping the conversation alive, then continuing from where you left off (resume with SEQ). The "give me a second" pause keeps your place — the listener (the memory/subordinate) knows you're still talking and stays ready for the rest. That's BUSY: a pause that keeps the burst alive, versus terminating and restarting. And it's your pause (the speaker's / master's) — different from the listener asking you to wait (the slave's wait state / HREADY low), which is the listener needing a moment, not you.

This captures BUSY: "give me a second, I'm still talking" = BUSY (master pause, burst alive); stopping and walking away = terminating the burst (IDLE); continuing from where you left off = resuming with SEQ; the speaker pausing vs the listener asking to wait = BUSY (master-side) vs HREADY low (slave-side). The pause keeps your place; ending loses it.

Watch BUSY pause and resume a burst:

The model's lesson: BUSY is "give me a second, I'm still going" — a master pause that keeps the burst alive and resumes from where it paused. In the waveform, the BUSY cycle paused the burst (no data, address held at A+8), and the SEQ resumed it at A+8 — the burst continued, not restarted. The pause kept the place.

4. Real Hardware Perspective

In hardware, the master drives HTRANS=BUSY when its data path isn't ready for the next beat, holding the next beat's address, and the subordinate treats a BUSY cycle as a no-op (no data transfer) while keeping the burst context — resuming on the next SEQ.

The master's BUSY logic comes from its data-readiness: if the master's source (a FIFO, a buffer, an internal pipeline) isn't ready to provide/accept the next beat this cycle, the master drives BUSY instead of SEQ. It continues driving BUSY (holding the next address) until its source is ready, then drives SEQ to resume. So BUSY is the master's "data not ready" state expressed on HTRANS. In hardware, this is a small control decision: SEQ if the next beat's data is ready, BUSY if not. A master that can always sustain back-to-back beats never needs BUSY; one with a bursty source uses BUSY to bridge the gaps.

The subordinate's BUSY handling is to treat the BUSY cycle as a non-transferring cycle while retaining the burst context. On seeing HTRANS=BUSY, the subordinate does not transfer data (no read/write happens) but keeps its burst state (it knows the burst is paused, not ended). When the next SEQ arrives, it resumes processing the burst from where it paused. So the subordinate distinguishes BUSY (pause, retain context) from IDLE (end, drop context) — both are non-transferring, but BUSY keeps the burst alive. This is why the subordinate must handle BUSY as a distinct case: a non-transferring cycle that isn't the end of the burst. A subordinate that confused BUSY with IDLE (and dropped the burst context) would mishandle the resumption.

The memory prefetch is preserved through BUSY: because the burst isn't terminated, the memory controller can keep its prefetch state through the BUSY pause — it knows the burst will resume, so it holds its opened row / prefetched data, ready for the resuming beats. So BUSY lets the memory ride through the pause without resetting its optimization. This is a key benefit of BUSY over terminate-and-restart: the prefetch survives the pause. If the master had terminated and restarted, the memory would reset and re-prefetch. So BUSY's preservation of the burst (and thus the prefetch) is its hardware advantage — the pause is cheap, the restart would be expensive.

A hardware note on BUSY rules: BUSY appears between beats of a burst (after a NONSEQ or SEQ, before the next SEQ). A burst should not end on a BUSY — BUSY is a pause, so it must be followed by the resumption (SEQ) or, for the burst to end, the proper termination (IDLE/NONSEQ) after the burst's beats. Also, BUSY is typically used within a burst the master is committed to completing — it's a momentary pause, not an indefinite stall. So in hardware, BUSY is inserted as needed between beats and always followed by resumption, keeping the burst well-formed. (The exact rules around BUSY at burst boundaries are spec details, but the core idea is: BUSY pauses between beats, the burst resumes.)

5. System Architecture Perspective

At the system level, BUSY enables rate-mismatched masters to sustain bursts — masters whose data rate doesn't perfectly match the bus can pause and resume rather than fragmenting their transfers — and it cleanly separates master-side flow control (BUSY) from slave-side flow control (wait states).

The rate-mismatch use case is BUSY's main value: a master whose data source is bursty (not ready every cycle) — a DMA from a FIFO that occasionally empties, a master with an internal pipeline that has gaps — can use BUSY to pause during the gaps and resume, keeping its burst intact. So BUSY lets such masters sustain logical bursts despite physical data gaps. Without BUSY, these masters would have to fragment their transfers into many short bursts (terminate-and-restart at each gap), losing efficiency. So BUSY exists to support masters whose data availability is imperfect — a common real situation. The system benefits because these masters keep their bursts (and the associated prefetch and amortization) rather than fragmenting.

The master-vs-slave flow-control separation is a clean architectural property. The bus has two independent flow-control mechanisms: BUSY (master-side — the master not ready, on HTRANS) and wait states / HREADY low (slave-side — the slave not ready, on HREADY). These are orthogonal: a transfer can be paused by the master (BUSY) or stretched by the slave (HREADY low), independently.

So the system has bidirectional flow control: either side can pause the bus when it's not ready, via its own mechanism. This separation is clean and complete — the master controls its readiness via HTRANS (BUSY), the slave via HREADY (wait states), and they compose (both can happen). So at the system level, BUSY completes the flow-control picture: master-side pausing, complementing the slave-side pausing of Module 6. This bidirectional flow control is what lets the bus handle both a not-ready master and a not-ready slave — each with its own signal, cleanly separated. Understanding BUSY as the master-side counterpart to wait states is the key architectural insight: the bus paces to whichever side is the bottleneck, via the appropriate mechanism.

6. Engineering Tradeoffs

BUSY embodies the pause-don't-restart, separate-master-flow-control design.

• BUSY (pause) vs terminate-and-restart. BUSY lets a master pause through a momentary stall while keeping the burst (preserving prefetch, sequence) at the cost of a non-transferring cycle. Terminate-and-restart loses the burst's benefits (reset prefetch, new NONSEQ, re-arbitration). For momentary stalls, BUSY is far more efficient.
• Master-side BUSY vs slave-side wait. Separating master-not-ready (BUSY) from slave-not-ready (HREADY low) gives clean, orthogonal flow control — each side pauses via its own signal. Conflating them would be ambiguous. AHB separates them — the bottleneck side pauses via its mechanism.
• Hold next address vs go idle. BUSY holding the next beat's address keeps the burst positioned for seamless resumption, at the minor cost of driving the address during the pause. Going idle would lose the position. Holding the address makes resumption clean.
• Distinct BUSY value vs reusing IDLE. A distinct BUSY (vs IDLE) lets the protocol express "pause without ending" — IDLE would end the burst. The extra HTRANS value is worth it: it enables in-burst pausing.

The throughline: BUSY is a master-inserted pause inside a burst — no data, next address held, burst not terminated, resumes with SEQ. It lets a rate-mismatched master ride through momentary data stalls without fragmenting its burst (preserving prefetch and sequence), and it cleanly separates master-side flow control (BUSY) from slave-side flow control (wait states / HREADY low). The cost (a non-transferring cycle, a distinct HTRANS value) is small relative to the benefit of sustaining bursts through stalls. BUSY completes the HTRANS burst vocabulary and the bus's bidirectional flow control.

7. Industry Example

Trace BUSY in a rate-mismatched master.

A DMA engine streams data from a source FIFO that occasionally empties, issuing a long INCR burst.

• The burst streams. The DMA issues an INCR burst, streaming beats from its source FIFO — NONSEQ, then SEQ beats, back-to-back, as long as the FIFO has data. The memory controller prefetches ahead, streaming efficiently.
• The FIFO momentarily empties — BUSY. At some point, the source FIFO momentarily runs dry (the upstream producer paused). The DMA isn't ready with the next beat's data. Instead of terminating the burst (which would reset the memory's prefetch and require a restart), the DMA drives BUSY — pausing the burst. During BUSY, no data transfers, and the DMA holds the next beat's address. The memory controller, seeing the burst paused (not ended), keeps its prefetch state, ready to resume.
• The FIFO refills — resume. When the source FIFO refills, the DMA drives SEQ to resume the burst from where it paused — continuing the beats seamlessly. The memory controller, having held its prefetch, resumes streaming. The burst continued through the stall, preserving the sequence and prefetch.
• The efficiency win. Had the DMA terminated the burst at the FIFO-empty (and restarted when refilled), it would have: reset the memory's prefetch (re-opening the row, re-prefetching), issued a new NONSEQ (re-establishing the burst), and possibly re-arbitrated. BUSY avoided all that — the pause was cheap, the restart would have been expensive. So BUSY let the DMA ride through the FIFO stall efficiently.
• A slave-side pause, separately. Independently, suppose the memory (slave) needs more time on a beat — it drives HREADY low (a wait state, Module 6). This is a slave-side pause, distinct from the DMA's BUSY. The bus handles both: BUSY when the DMA isn't ready, HREADY low when the memory isn't ready. Two independent flow-control mechanisms, each pausing the bus from its side.
• Diagnosing a pause. If an engineer sees the bus paused mid-burst, they check which signal: HTRANS=BUSY means the DMA (master) paused; HREADY low means the memory (slave) is stretching. The two are diagnosed differently — BUSY points to the master's data source, HREADY low to the slave's speed.

The example shows BUSY enabling a rate-mismatched master (a DMA with a bursty FIFO source) to sustain its burst through momentary stalls — pausing with BUSY and resuming, preserving the sequence and prefetch, far more efficient than terminate-and-restart. And it shows BUSY (master-side) cleanly separated from wait states (slave-side): two independent ways the bus pauses, diagnosed by which signal. BUSY is the master's tool for pausing without losing the burst.

8. Common Mistakes

9. Interview Insight

BUSY is a discriminating interview topic — the master-side-vs-slave-side distinction and the pause-not-terminate point are the signals.

The answer that lands explains BUSY and contrasts it with wait states: "HTRANS=BUSY is a master-inserted pause inside a burst — it means the master is still in the burst but isn't ready with the next beat, maybe because its source FIFO momentarily emptied. During a BUSY cycle, no data transfers, the master holds the next beat's address, and crucially the burst is not terminated — it resumes with a SEQ beat when the master is ready. So BUSY lets a master pause mid-burst without losing the sequence, which is much more efficient than terminating and restarting (that would reset the memory's prefetch and need a new NONSEQ). The key distinction: BUSY is master-side flow control — the master not ready, signalled on HTRANS — whereas a wait state, HREADY low, is slave-side — the slave not ready, signalled on HREADY. Both pause the bus, but from opposite sides. So the bus has bidirectional flow control: the master pauses via BUSY, the slave via wait states." The pause-not-terminate semantics, the master-side-vs-slave-side distinction, and the efficiency-over-restart point are the senior signals.

10. Practice Challenge

Reason from BUSY's pause semantics.

1. Define BUSY. Explain what a BUSY cycle is and what happens during it.
2. Pause vs terminate. Explain how BUSY differs from terminating a burst.
3. Read the waveform. From Figure 2, identify the BUSY cycle, what's held, and where the burst resumes.
4. BUSY vs wait state. Contrast BUSY (master-side) with HREADY low (slave-side).
5. Efficiency. Explain why BUSY is more efficient than terminate-and-restart for a momentary stall.

11. Key Takeaways

• HTRANS=BUSY is a master-inserted pause inside a burst — "I'm still in the burst but not ready with the next beat."
• During BUSY: no data transfers, the master holds the next beat's address, and the burst is not terminated — it resumes with a SEQ beat when the master is ready.
• BUSY pauses, terminate ends — unlike driving IDLE/NONSEQ (which ends the burst), BUSY keeps the burst alive, preserving the sequence and the memory's prefetch.
• BUSY is master-side flow control; wait states (HREADY low) are slave-side — BUSY = master not ready (HTRANS), HREADY low = slave not ready (HREADY). Opposite sides, both pause the bus.
• A subordinate retains the burst context through BUSY (pause, no transfer) — distinct from IDLE (end, drop context). Confusing them mishandles the resumption.
• BUSY lets rate-mismatched masters sustain bursts through momentary data stalls (a DMA with a bursty FIFO source) — far cheaper than terminate-and-restart, which resets prefetch and needs a new NONSEQ.

12. What Comes Next

You now understand how a burst pauses (BUSY) and ends (chapter 8.10). The final chapter of the module catalogues the bugs:

• 8.12 — Common Burst Bugs (coming next) — the recurring burst mistakes (wrong wrap, lost beat, bad SEQ, mishandled termination/BUSY) and their signatures.

To revisit how bursts end, see Burst Termination. For the HTRANS values, see HTRANS, BUSY Transfers, and SEQ Transfers. For the slave-side pause BUSY contrasts with, see Slave-Inserted Wait States. For the burst overview, Burst Overview. For the broader protocol map, see the AMBA family overview.