Data Phase Extension

Chapters 6.2–6.4 covered the mechanism of a wait state — the subordinate inserting it, the manager holding through it, the address/control contract. This chapter takes the timing/pipeline view: what a wait state does to the two-phase pipeline as a whole. The key insight is that a wait does not just stretch one transfer's data phase in isolation — it stretches the pipeline uniformly. The current transfer's data phase and the next transfer's overlapping address phase extend by the same amount, in lockstep. The pipeline slows but never breaks: the address-leads-data relationship, the transfer ordering, and the two-phase overlap structure all survive the wait intact. A wait changes only duration, never structure.

1. What Is It?

Data phase extension is what a wait state does to the pipeline: it lengthens the current transfer's data phase from one cycle to (N+1) cycles for N wait states — and, because the pipeline overlaps transfers, it lengthens the next transfer's address phase by the same amount, in lockstep.

The two phases extend together because they overlap in time (chapter 5.1): the current transfer's data phase occupies the same cycles as the next transfer's address phase. So when a wait freezes those cycles, both phases are extended by the wait — the data phase of the current transfer and the address phase of the next transfer, by exactly the same number of cycles.

So data phase extension is best understood not as "one transfer's data phase got longer" but as "the pipeline stretched at that point" — both the current data phase and the concurrent next address phase grow together. The pipeline is like an accordion: a wait pulls it wider at that point, extending the overlapping phases in lockstep, but the structure (the fold pattern) is unchanged. This is why a wait slows the pipeline uniformly rather than corrupting it.

2. Why Does It Exist?

Data phase extension — both phases stretching together — exists as a consequence of the pipeline's overlap and the bus-wide HREADY: because the current data phase and the next address phase occupy the same cycles, and HREADY freezes all participants together, both phases are necessarily extended by the same wait.

It is not a separate mechanism the bus implements; it is what must happen given two facts established earlier. First, the two phases overlap (chapter 5.1): the next transfer's address phase runs concurrently with the current transfer's data phase. Second, HREADY is bus-wide (chapter 6.1): when it goes low, everything freezes — both the current data phase and the next address phase are held. Put those together and the conclusion is forced: a wait freezes the overlapping cycles, so both the data phase and the concurrent address phase extend by the same amount. Data phase extension exists because the overlap plus the shared freeze make the two phases stretch in lockstep — they cannot do otherwise.

The reason this matters (rather than being a mere curiosity) is that it is what keeps the pipeline correct through a wait. If only the data phase extended but the next address phase advanced anyway, the next transfer would race ahead into its data phase before the current one finished — breaking the pipeline. Because both extend together, the next transfer stays correctly one step behind: it waits in its (extended) address phase until the current data phase completes, then advances. So the lockstep extension is what preserves the pipeline's ordering and overlap through the wait. It exists, in effect, to keep the pipeline coherent while slowed.

This is why the address-leads-data invariant survives the wait. Normally each transfer's address phase leads its own data phase by one pipeline step (chapter 5.2). A wait stretches the phases but stretches them together, so each transfer's address still leads its own data by one step — the lead is preserved because both sides of it extended equally. So data phase extension preserves the fundamental timing relationship of AHB; it changes the pace of the pipeline without changing its shape. That preservation is exactly why a wait is safe.

3. Mental Model

Model the pipeline as a marching column where a wait is the whole column pausing in step — everyone halts together and resumes together, so the spacing between marchers never changes.

A marching column (the pipeline) moves forward one step per beat (per cycle). Each marcher (a transfer) is one step behind the one ahead (address phase leads data phase by one step). When a wait happens, the whole column pauses (HREADY low freezes everyone) — not just one marcher. Everyone holds their position; the spacing between them is unchanged. When the wait ends (HREADY high), the whole column steps forward together again. Because everyone paused and resumed together, the ordering and spacing are perfectly preserved — the column just took longer to cover the ground. No marcher got out of step; no one collided.

This captures data phase extension precisely: the whole column pausing together = both phases (current data, next address) extending in lockstep; the spacing unchanged = the address-leads-data lead preserved; the taking longer = throughput lost. The wait is a synchronized pause of the whole pipeline, which is why it preserves structure — exactly as a marching column staying in step through a pause.

Watch the pipeline stretch through a wait:

The model's lesson: a wait is the whole pipeline pausing in step — both overlapping phases extend together, so the spacing (address-leads-data) never changes. In the waveform, A2 and D1 hold together through the wait and advance together on HREADY high — the column stayed in step.

4. Real Hardware Perspective

In hardware, the lockstep extension is automatic: because all the pipeline's stage registers are gated by the same bus-wide HREADY, they all hold together when HREADY is low and all advance together when it is high — the pipeline stretches uniformly by construction.

The pipeline's state lives in registers — the address-phase registers (holding the current address-phase transfer) and the data-phase registers/logic (holding the current data-phase transfer). All of these are enabled by the same HREADY (the clock-enable framing, chapters 6.1, 6.3). So when HREADY is low, every pipeline stage holds; when high, every stage advances. There is no way for one stage to advance while another holds — they share the enable. This is precisely why both phases extend by the same amount: they are gated by one signal. The uniform stretch is not coordinated by extra logic; it is the natural result of a single shared clock-enable on all pipeline stages.

This shared-enable construction is what makes the pipeline safe under arbitrary waits: however long HREADY stays low, every stage holds in lockstep, so the pipeline's contents stay correctly aligned and resume cleanly. The hardware cannot get the pipeline out of step via a wait, because there is no mechanism to advance stages independently — they all gate on HREADY. So a designer gets the lockstep extension for free by gating all pipeline stages with HREADY, which is the standard construction. A pipeline that gated stages with different enables could get out of step — but AHB's single HREADY precludes that.

The address-leads-data preservation is likewise structural: the one-cycle lead exists because the address register feeds the data stage one cycle later (chapter 5.2). When both registers hold for the same N extra cycles, the lead between them is unchanged — register A still feeds register D the same one step later, just N cycles further along. So the lead is preserved by the same shared-enable construction that causes the lockstep extension. In hardware, the invariant survives because the registers that establish it hold together.

A hardware nuance worth noting: the read data path also extends with the pipeline — for a read, HRDATA becomes valid on the completing (HREADY-high) cycle at the end of the extended data phase (chapter 5.4). So the data-phase extension is where read latency lives: the extra cycles are the subordinate producing the data, and the manager captures it at the stretched data phase's end. The extension and the read-data-valid timing are the same phenomenon viewed from the data path: the data phase is long because the subordinate needs those cycles, and the data is valid at its end.

5. System Architecture Perspective

At the system level, data phase extension is the precise statement of how wait states cost throughput — and the fact that the pipeline only slows (never breaks) is what makes wait states a safe, composable performance knob rather than a correctness hazard.

The throughput cost is exactly the extension (chapters 4.6, 6.2): each cycle of data-phase extension is a cycle the pipeline did not advance — a lost transfer slot. So a workload's throughput loss is the sum of all its data-phase extensions (the total wait cycles). Because the extension is uniform (the whole pipeline pauses), the cost is clean to reason about: N wait cycles = N lost transfer slots, regardless of which transfer caused them. This is why AHB throughput modeling reduces to counting wait cycles (data-phase extensions) — the pipeline's uniform stretch makes the accounting simple.

The slows-but-never-breaks property is architecturally important because it means wait states are safe to introduce anywhere. A slow subordinate inserting waits cannot corrupt the pipeline or other transfers — it only slows the bus while its transfer extends. So adding a slow subordinate to a system is a performance decision, not a correctness risk: it will slow the bus during its accesses but cannot break anything. This safety is what lets architects freely mix subordinate speeds (chapter 6.2) — the worst a slow subordinate can do is extend the pipeline (cost throughput), never derail it. The structural preservation under waits is the foundation of that freedom.

For waveform analysis and verification, the preserved invariant is a powerful tool: when reading any AHB waveform, the address-leads-data diagonal still holds through wait states — each transfer's data is one (extended) step after its address. So an engineer debugging a waveform can always pair each address with its data by following the pipeline, even across waits, because the structure is preserved (chapter 5.7). This is why "the pipeline only stretches" is not just reassuring but useful: it means the reading method (number cycles, pair address with the following data, track HREADY) works uniformly, waits included. The invariant's survival is what makes waveform reading tractable.

6. Engineering Tradeoffs

Data phase extension reflects AHB's synchronized-pipeline design.

• Uniform stretch vs independent stages. Gating all pipeline stages with one HREADY makes the pipeline stretch uniformly (safe, simple, structure-preserving) at the cost that the whole pipeline pauses together (no stage can make progress while another waits). Independent per-stage enables could let some stages advance during a wait but would risk the pipeline getting out of step. AHB chooses the uniform stretch — safety and simplicity over partial progress.
• Slows-never-breaks vs faster-but-fragile. AHB's wait states only slow the pipeline, never corrupt it — a robust, composable property. A more aggressive design might extract more throughput under contention but with fragile timing. AHB favors the robust, always-correct behaviour, consistent with its simplicity goals.
• Preserving address-leads-data vs collapsing phases. Keeping the one-step lead through waits preserves a uniform, readable pipeline structure. Collapsing or reordering phases under waits might save a cycle in edge cases but would destroy the clean structure. AHB preserves the invariant — predictability over micro-optimization.
• Whole-pipeline pause vs out-of-order progress. The synchronized pause matches AHB's in-order, single-outstanding-transfer model (chapter 5.6). Out-of-order progress during waits is what AXI provides, at the cost of large complexity. AHB's synchronized stretch is the simpler choice that fits its model.

The throughline: a wait stretches the whole pipeline uniformly because all stages share one HREADY — preserving structure and ordering, costing only throughput. The tradeoff is that the entire pipeline pauses together (no partial progress), accepted because it makes wait states safe, composable, and simple to reason about — the worst a wait can do is slow the bus, never break it.

7. Industry Example

Trace data phase extension through a back-to-back sequence with a slow transfer in the middle.

A processor issues three back-to-back reads: fast SRAM (R1), slow flash (R2), fast SRAM (R3), pipelined.

• R1 (no wait) — pipeline advances normally. R1's address phase in one cycle, its data phase the next; meanwhile R2's address phase overlaps R1's data phase. SRAM is fast, so R1's data phase is one cycle — the pipeline advances. Address-leads-data holds: R1's address led its data by one step.
• R2 (multi-wait) — the pipeline stretches. R2 hits the slow flash, which inserts several wait states. Now R2's data phase extends over several cycles — and R3's address phase, which overlaps R2's data phase, extends in lockstep (R3's address is held). The whole pipeline pauses through R2's wait: D(R2) and A(R3) stretch together. The processor holds R3's address steady, holds R2's read pending, and waits. The pipeline stretched at R2; it did not break.
• R2 completes, R3 advances. When flash asserts HREADY high, R2's read completes (data valid on that cycle), and R3 — held in its extended address phase — advances into its data phase. R3's address still led its data by one step; the invariant survived the stretch. The pipeline resumes its normal pace.
• R3 (no wait) — back to normal. R3 hits fast SRAM, one-cycle data phase, pipeline advances normally again. The stretch was localized to R2's wait; before and after, the pipeline ran at pace.
• The throughput accounting. The sequence took (normal time + R2's wait cycles). The only cost was R2's data-phase extension — those wait cycles are the lost throughput. R1 and R3 were unaffected in structure; the pipeline simply paused during R2 and resumed. The cost is clean: it equals R2's wait count.

The example shows data phase extension as a localized, structure-preserving stretch: the pipeline ran at pace for R1, paused (stretched both R2's data and R3's address together) during R2's wait, and resumed at pace for R3. The address-leads-data invariant held throughout, the ordering held, and the only cost was the wait cycles. A slow transfer slowed the pipeline without breaking it — exactly the safe behaviour that lets fast and slow subordinates mix.

8. Common Mistakes

9. Interview Insight

The pipeline view of wait states is a discriminating interview question — it tests whether you understand the overlap, not just the single-transfer mechanism.

The answer that lands takes the pipeline view: "A wait state extends the current transfer's data phase from one cycle to N+1 cycles — but because AHB pipelines, the next transfer's address phase overlaps that data phase, so it extends in lockstep too. The whole pipeline stretches uniformly. Crucially, the structure is preserved: the address-leads-data relationship still holds (both phases extended equally), the transfer ordering is unchanged, the two-phase overlap is intact. A wait changes only the duration, never the structure — the pipeline slows but never breaks or reorders. In hardware, this is automatic because all pipeline stages share one HREADY enable." The lockstep-extension point and the slows-not-breaks framing are the senior signals.

10. Practice Challenge

Reason from the pipeline view.

1. State the extension. Describe what a wait state extends — and why two phases, not one.
2. Read the waveform. From Figure 2, identify the two phases that extend together and confirm the address-leads-data lead is preserved.
3. Explain the lockstep. Why do the current data phase and the next address phase extend by the same amount?
4. Trace a sequence. For the R1/R2/R3 example, describe what stretches during R2's wait and what the throughput cost is.
5. Apply the property. Explain why "slows but never breaks" makes adding a slow subordinate a performance decision, not a correctness risk.

11. Key Takeaways

• A wait state extends the current transfer's data phase to (N+1) cycles — and, because the pipeline overlaps, the next transfer's address phase extends in lockstep by the same amount.
• The two phases stretch together because they share the frozen cycles and the bus-wide HREADY freezes all participants at once — the pipeline stretches uniformly.
• The pipeline slows but never breaks: the address-leads-data relationship, the transfer ordering, and the two-phase overlap are all preserved. A wait changes only duration, never structure.
• In hardware this is automatic — all pipeline stages share one HREADY enable, so they hold and advance in lockstep, preserving the invariant by construction.
• Throughput cost is exactly the total extension (wait cycles = lost transfer slots) — the uniform stretch makes the accounting clean.
• "Slows but never breaks" makes slow subordinates safe to mix — adding one is a performance decision, not a correctness risk, and it keeps waveform reading and verification tractable across waits.

12. What Comes Next

You now understand what a wait does to the pipeline. The next chapter examines where HREADY itself comes from:

• 6.6 — HREADY vs HREADYOUT (coming next) — why subordinates output HREADYOUT, how the interconnect aggregates it into the bus-wide HREADY each participant observes, and the input-vs-output distinction.

To revisit the foundations, see The Two-Phase Pipeline, Address Phase Leads Data Phase (the invariant preserved here), and Slave-Inserted Wait States. For reading pipelines off waveforms, see Phase Waveform Interpretation. For the broader protocol map, see the AMBA family overview.