The myth that APB pipelines — that the next transfer's SETUP overlaps the current transfer's ACCESS — is false: APB is architecturally non-pipelined, so SETUP(N+1) cannot begin until ACCESS(N) completes with PREADY, and the belief is almost always a confusion between legal back-to-back transfers and true pipelining. You have already seen why APB is not pipelined — the structural cause — and how throughput falls out of that. This chapter attacks the myth head-on: it names the exact claim engineers make ("just overlap the next SETUP with this ACCESS to save the two-cycle floor"), proves on the waveform that no such overlap exists, and — the load-bearing insight — draws the crisp line between back-to-back (two serial transfers with zero idle between them, entirely legal) and pipelining (two transfers whose phases overlap in the same cycle, which APB cannot represent). Get that distinction right and the throughput cap 1 / (2 + w) stops being a limitation to fight and becomes a number you can defend.

1. Problem statement

The problem is refuting a specific, plausible-sounding claim — that an APB manager can pipeline transfers by presenting the next address during the current access — and doing it precisely enough that an engineer stops trying to design around a cap that is structural, not tunable.

The myth has a seductive shape. On AHB and AXI, the address phase of one transfer overlaps the data phase of the previous one, so a burst approaches one transfer per cycle. Someone who knows those buses looks at APB's 2 + w per-transfer cost, sees a fixed two-cycle floor, and reasons: surely I can hide the SETUP cycle of transfer N+1 underneath the ACCESS cycle of transfer N, the way AHB hides its address phase — recovering roughly a cycle per transfer. That reasoning is wrong for APB, and it is wrong for a precise structural reason:

• There is no second address in flight. An APB manager drives exactly one PADDR / PWRITE / PWDATA / PSEL set, held stable across SETUP and ACCESS until PREADY. There is no staged "next address" register behind it, so there is nothing to present during the current ACCESS — the wires are still occupied by the in-flight transfer.
• PENABLE is a single, shared phase bit. PENABLE is low in SETUP and high in ACCESS for the one transfer on the bus. It cannot simultaneously be low (SETUP of N+1) and high (ACCESS of N) — one wire, one value per cycle — so the two phases are mutually exclusive by construction.
• The confusion is back-to-back versus pipelined. What people see and call "pipelining" is two transfers with no idle cycle between them: ACCESS(N) completes, and on the very next cycle SETUP(N+1) begins. That is back-to-back — still fully serial, still 2 + w each. Pipelining would need those two phases to share a cycle. They never do.

So the job is to state the myth, prove the non-overlap directly on PSEL / PENABLE / PREADY, separate back-to-back from pipelining once and for all, and show why the throughput ceiling 1 / (2 + w) is a consequence of the myth being false — per AMBA APB (IHI 0024C) §3.1, which defines the two-phase transfer that leaves nothing to overlap.

2. Why previous knowledge is insufficient

You have the structural cause and the cost model already — but neither, on its own, kills this specific myth, because the myth survives by mislabelling something legal.

• Why APB is not pipelined gave the cause, not the refutation. That chapter explains why the FSM cannot overlap — one address set, slave held for the whole transfer. This chapter takes the next step: it confronts the person who says "but I can still overlap the SETUP" and shows on the waveform that the thing they think is overlap is actually a zero-idle back-to-back sequence. Knowing the cause is not the same as being able to dismantle the specific false claim.
• Throughput gave the number, not the boundary. You learned throughput is f_clk / (2 + N_avg) with no burst bonus. But why is there no burst bonus? Because the pipeline the myth assumes does not exist. This chapter supplies the missing link between "no pipeline" and "no amortisation," and reframes the cap as 1 / (2 + w) cycles-per-transfer so the myth's promised savings can be shown to be exactly zero.
• You have seen back-to-back transfers but never had them distinguished from pipelining. The transfer lifecycle and single-cycle transfer chapters show one transfer end and the next begin. What was never made explicit is that "next begins immediately" is not "phases overlap." That single distinction is the whole myth, and until it is drawn sharply the belief keeps regenerating.

The model to add is a refutation instrument: a way to look at any APB trace, recognise the difference between abutting-serial and overlapping, and prove the overlap the myth claims is not merely absent but unrepresentable on the three signals that define the transfer.

3. Mental model

The model: APB is a turnstile, not an escalator. A turnstile admits exactly one person, waits for them to pass fully through, and only then releases for the next — one body in the mechanism at a time. An escalator (AHB/AXI) has many people on the steps at once, each at a different stage, all moving together — that is a pipeline. The myth is looking at a busy turnstile — people stepping through one immediately after another with no gap — and mistaking the fast cadence for an escalator. It is not: at every instant there is still exactly one person in the turnstile.

Three refinements make the distinction exact:

• Back-to-back is temporal adjacency; pipelining is phase overlap. Back-to-back means SETUP(N+1) starts the cycle after ACCESS(N) completes — adjacent in time, zero idle, but the phases never share a cycle. Pipelining means SETUP(N+1) runs in the same cycle as ACCESS(N) — the phases co-occupy the bus. APB supports the first and cannot express the second. The test is simple: is there any single cycle in which two distinct transfers are both live? On APB the answer is always no.
• PENABLE is the tell. Trace PENABLE: it is low (SETUP), then high (ACCESS), then — for a back-to-back — low again (SETUP of the next). A pipeline would need PENABLE to be simultaneously the ACCESS of N and the SETUP of N+1, i.e. one wire holding two phase meanings in one cycle. Impossible. So PENABLE alone disproves the myth: it is a single per-transfer phase marker, not a per-lane one.
• Zero idle is the most you can do, and it is not pipelining. The myth promises savings beyond zero idle — hiding a phase. But zero idle back-to-back is already the tightest legal cadence: 2 + w cycles per transfer, one after another. There is no representable state tighter than that, so the myth's promised cycle-per-transfer saving is exactly zero. The cap 1 / (2 + w) is what "tightest legal cadence" numerically equals.

4. Real SoC implementation

In RTL the myth is disproved by what the manager FSM cannot even encode. There is no state, and no set of drive equations, in which a fresh transfer's SETUP coexists with an in-flight ACCESS — because PENABLE and the single address set are shared. The block below shows the serial FSM, the back-to-back path (legal, no overlap), and — in comments — exactly what a pipeline would have demanded and why APB has none of it.

// APB manager FSM. A single transfer is self-contained: SETUP then ACCESS,
// and the NEXT transfer's SETUP cannot begin until THIS ACCESS completes (PREADY).
// There is no state where SETUP(N+1) and ACCESS(N) coexist -> no pipelining.
typedef enum logic [1:0] { IDLE, SETUP, ACCESS } apb_state_t;
apb_state_t state, next;
 
always_comb begin
  next = state;
  unique case (state)
    IDLE:   if (req)            next = SETUP;    // a new transfer may start
    SETUP:                      next = ACCESS;   // SETUP is always exactly one cycle
    ACCESS: if (pready)                          // completion of transfer N ...
              next = req ? SETUP : IDLE;         // ... ONLY now can N+1's SETUP begin.
            // if !pready: stay in ACCESS (wait state). N+1 still cannot start;
            // the single address/PENABLE set is owned until PREADY.
  endcase
end
 
always_ff @(posedge pclk or negedge presetn)
  if (!presetn) state <= IDLE;
  else          state <= next;
 
// One address/control set + one PENABLE, held for the WHOLE transfer.
// PENABLE cannot be SETUP(N+1)=0 and ACCESS(N)=1 in the same cycle -> no overlap.
assign psel    = (state == SETUP) || (state == ACCESS);
assign penable = (state == ACCESS);
// paddr/pwrite/pwdata load at SETUP, hold until PREADY. No second, staged address.
 
// BACK-TO-BACK (legal, still serial): ACCESS(N) completes on PREADY, and on the
// NEXT cycle SETUP(N+1) starts. Zero idle, but the two phases never share a cycle.
//   cycle k   : ACCESS(N),  penable=1, pready=1   <- N completes here
//   cycle k+1 : SETUP(N+1), penable=0             <- N+1 starts here, NOT overlapped
//
// WHAT PIPELINING WOULD HAVE REQUIRED (and why it would not be APB):
//   - a SECOND, staged address register so N+1's PADDR could drive during ACCESS(N);
//   - DECOUPLED address-accept vs data-ready handshakes instead of one PREADY;
//   - a PENABLE-equivalent PER lane so two phases could co-occupy a cycle.
// AHB/AXI have exactly this decoupling; APB (IHI 0024C, section 3.1) omits all of
// it, which is precisely why its two phases are serial. See /protocols/apb/apb-vs-ahb-vs-axi.

Two facts settle the myth. First, the non-overlap is unrepresentable, not merely disallowed. There is no guard that "blocks" an early SETUP — the FSM simply has no encoding for two live transfers, because PENABLE is one bit and the address set is one register. You cannot pipeline a bus whose signals cannot even express two simultaneous phases. Second, back-to-back is the tightest legal cadence and it saves nothing the myth promised. In the annotated back-to-back above, SETUP(N+1) lands on the cycle after PREADY of N — adjacent, zero idle — but each transfer still costs its full 2 + w. So the per-transfer cost, and therefore the throughput cap, is exactly:

throughput (transfers/cycle) = 1 / (2 + w), where w is the wait-state count of the ACCESS phase (w = 0 for a zero-wait slave).

The peak 0.5 transfer/cycle — one every two cycles — is the ceiling a pipelined bus would beat (approaching 1.0). APB cannot reach it because the SETUP the myth wants to hide is a real, un-overlappable cycle. That the peak is exactly 1 / (2 + w) is the proof that the myth's savings are zero.

5. Engineering tradeoffs

The trade here is not "pipeline or not" — APB gives you no such knob — it is understanding that the absence of the pipeline is the price paid for the simplicity you chose. The table separates the two things the myth conflates and shows what each actually delivers.

Two throughlines. First, back-to-back already gives you everything legal — zero idle — and it is not pipelining. The myth promises a saving past zero idle by hiding a phase; that saving is exactly zero because the phase to hide is un-overlappable. Second, the only way to actually get the myth's throughput is to stop using APB. Real overlap needs the staged address, decoupled handshakes, and per-lane phase signalling that define AHB/AXI (see APB vs AHB vs AXI); adding them to APB rebuilds AHB and forfeits the trivial slave and tiny gate count you put the peripheral on APB to get. So the honest engineering position is: quote 1 / (2 + w), keep the cadence tight with zero-idle back-to-back, and move bursty traffic to a pipelined bus — never pretend the cap can be tuned away, because it is structural, and its effect on real designs is a hard ceiling on bus utilisation.

6. Common RTL mistakes

7. Debugging scenario

The signature "bug" is not RTL — it is an architect who designed against the myth: they budgeted a configuration region assuming pipelined APB would overlap SETUP with ACCESS, promised a throughput their bus cannot deliver, and now the boot sequence misses its window.

• Observed symptom: a block of 8 back-to-back register writes was budgeted at ~9 cycles ("8 transfers pipelined, ~1 cycle each plus a startup") but measures ~16 cycles. Every write is functionally correct; only the aggregate is wrong — almost exactly 2× the budget. A downstream boot step that depended on the region being configured by cycle ~9 is late.
• Waveform clue: decompose the trace and look for a single cycle where two transfers are live. There is none. Each transfer shows PENABLE low for one cycle (SETUP), PENABLE high with PREADY high for one cycle (ACCESS completion, w = 0), and the next transfer's PENABLE-low SETUP begins only on the cycle after that PREADY. The expected overlap — SETUP of N+1 sharing the ACCESS cycle of N — is simply absent; what is there is textbook back-to-back at 2 cycles each, 8 × 2 = 16.
• Root cause: the budget assumed APB pipelines. It does not: one address set, one PENABLE, so SETUP(N+1) cannot coexist with ACCESS(N), and each transfer costs its full 2 + w. The architect confused the legal zero-idle back-to-back cadence with pipelining and expected a cycle-per-transfer saving that is structurally zero. The RTL is correct APB; the model was wrong.
• Correct RTL: there is nothing to fix in the RTL — the serial back-to-back behaviour is the spec. The fix is in the model and the plan: re-cost the region at transfers × (2 + w) (here 8 × 2 = 16, not 9), and if the boot window genuinely needs the transfers to overlap, move that traffic to a pipelined bus (AHB/AXI) or reduce the number of transfers (batch, or use a wider register). On APB, accept 1 / (2 + w) as the design point.
• Verification assertion: prove the overlap the myth assumes cannot occur — a fresh transfer's PENABLE-high ACCESS can never begin while the previous ACCESS is still unfinished, and no new SETUP appears mid-ACCESS. See §8 for the property. Pair it with a performance coverpoint that the back-to-back burst rate equals 1 / (2 + w), so any accidental over-optimistic model is caught as a coverage miss.
• Debug habit: when an APB region "runs at half the budgeted rate" with every transfer correct, do not hunt for a logic bug — audit the throughput model for a hidden pipeline assumption. Scan the waveform for a single cycle with two live transfers; if there is none (there never is), the budget assumed overlap that APB cannot do. Re-cost with 2 + w per transfer and decide between accepting the serial rate and moving the traffic off APB.

8. Verification perspective

Because the myth claims an overlap that is structurally impossible, verification's job is to prove the non-overlap holds on every back-to-back stream — that no two transfers are ever live in the same cycle, that a new transfer only begins out of a completed ACCESS, and that the measured cadence is exactly the 1 / (2 + w) cap.

• Assert no two transfers ever overlap. The core safety property: while an ACCESS is in flight (PENABLE high, PREADY low), the next cycle must still be that same ACCESS (PENABLE stays high) or the transfer ends (PSEL deasserts) — never a fresh PSEL-high / PENABLE-low SETUP of a new transfer. This proves the bus carries exactly one transfer at a time, which is the refutation of the pipeline myth.

// NO-OVERLAP: access N+1 cannot begin before access N completes.
// While in an unfinished ACCESS, the next cycle is still that ACCESS
// (PENABLE high) or the transfer ends (PSEL low) -- never a new SETUP.
ap_no_overlap: assert property (@(posedge pclk) disable iff (!presetn)
  (psel && penable && !pready) |-> ##1 (penable || !psel)
);
 
// PENABLE (access phase) of a NEW transfer must never rise while the
// previous access is still waiting -- i.e. PENABLE cannot restart mid-wait.
ap_penable_serial: assert property (@(posedge pclk) disable iff (!presetn)
  (penable && !pready) |-> ##1 penable
);
 
// SETUP of the next transfer only follows a COMPLETED access.
// A back-to-back SETUP (PSEL high, PENABLE low) must be preceded by
// a completing access (PENABLE && PREADY) the cycle before.
ap_setup_after_complete: assert property (@(posedge pclk) disable iff (!presetn)
  (psel && !penable && $past(psel && penable))
    |-> $past(penable && pready)
);

• Cover the tightest cadence and the cap. Functional coverage must include a stream of zero-idle back-to-back transfers (with and without wait states) and confirm the measured burst rate equals 1 / (2 + w) — no cycle is ever saved by overlap. A suite that only runs isolated transfers proves nothing about the myth; the back-to-back burst is exactly where a mistaken pipeline assumption would show up, so it must be covered explicitly with a cover for (penable && pready) ##1 (psel && !penable) ##1 (penable && pready) — completion, then a fresh SETUP, then the next completion.
• Cross-check against the formula. Bind a counter that increments on each (penable && pready) completion, sample over a fixed window, and assert the achieved cadence matches 1 / (2 + w) for the stream's w. If a zero-wait saturated stream ever measures faster than one transfer per two cycles, either the monitor is wrong or someone has (illegally) built overlap — both are bugs the assertion catches before silicon.

The point: verify that APB carries one transfer at a time (no overlap), that a new SETUP only follows a completed ACCESS, and that back-to-back streams run at exactly 1 / (2 + w) — so the non-pipelined guarantee is proven, and any resurrected "pipelined APB" assumption trips an assertion instead of a boot-time deadline.

9. Interview discussion

"Can APB be pipelined?" is a trap question — the interviewer wants to hear a clean "no" and the reason, and, crucially, whether you can tell back-to-back from pipelining, because that is the exact confusion the myth lives in.

Answer in three moves. First, the verdict and cause: no — APB is architecturally non-pipelined; it drives one address/control set and one PENABLE per transfer, held to PREADY, so SETUP(N+1) cannot coexist with ACCESS(N) — there is no cycle where two transfers are live (AMBA APB IHI 0024C §3.1). Second, the distinction that proves you actually understand it: what people mistake for pipelining is back-to-back — two transfers with zero idle between them, where the next SETUP begins the cycle after the previous PREADY. That is temporal adjacency, not phase overlap; the phases never share a cycle. Pipelining, as in AHB/AXI, overlaps the next transfer's address phase with the current data phase — and it needs a staged address register, decoupled handshakes, and per-lane phase signalling that APB deliberately omits. Third, the consequence: because there is no overlap, throughput is capped at 1 / (2 + w) transfers per cycle — 0.5 at zero waits — and back-to-back saves the idle between transfers but never the two-cycle floor within one. The senior flourish: "so if someone proposes pipelining APB to hit a throughput target, they're really proposing to stop using APB — the cap is structural, not a tuning knob, and bursty traffic belongs on AHB or AXI." Drawing the back-to-back-versus-pipeline line unprompted is what separates an engineer who has debugged an APB trace from one who has only read that "APB is slow."

10. Practice

1. State the myth and refute it. In three sentences, state the "overlap the next SETUP with the current ACCESS" claim and give the structural reason (single address set, single PENABLE) it is impossible — without using "pipeline" as the explanation itself.
2. Draw the line. Define back-to-back and pipelining precisely, and give the one-cycle test (is any single cycle occupied by two live transfers?) that distinguishes them on a waveform.
3. Cost a burst. For 8 zero-wait back-to-back transfers, give the true cycle count and the (wrongly) assumed pipelined count, and state the ratio and the per-transfer cost.
4. Compute the cap. Give 1 / (2 + w) for w = 0, 1, and 2, and state which one a pipelined bus would beat and by roughly how much.
5. Write the assertion. From memory, sketch the SVA that proves a new transfer's ACCESS (PENABLE high) can never begin while the previous ACCESS is still waiting on PREADY.

11. Q&A

12. Key takeaways

• The myth is false: APB cannot overlap the next transfer's SETUP with the current ACCESS. PENABLE is a single per-transfer phase bit and there is one address set held to PREADY, so no cycle can contain two live transfers. The overlap is unrepresentable, not merely disallowed (AMBA APB IHI 0024C §3.1).
• Back-to-back is not pipelining. Back-to-back is temporal adjacency — SETUP(N+1) begins the cycle after ACCESS(N) completes, zero idle. Pipelining is phase overlap — two transfers live in one cycle. APB does the first and structurally forbids the second. The test: is any single cycle occupied by two transfers? On APB, never.
• Zero-idle back-to-back is the tightest legal cadence and saves nothing the myth promised. It removes the idle between transfers but never the two-cycle floor within one, so each transfer still costs its full 2 + w.
• Throughput is capped at 1 / (2 + w) transfers per cycle — 0.5 at zero waits — precisely because there is no overlap to amortise the floor. That the cap equals 1 / (2 + w) is the proof the myth's saving is zero; a pipelined bus would beat it by approaching 1.0.
• "Pipelined APB" means AHB. Real overlap needs a staged address register, decoupled address/data handshakes, and per-lane phase signalling — exactly the machinery APB omits (see why APB is not pipelined and APB vs AHB vs AXI). If you need a pipeline, you have chosen the wrong bus, not found a defect in APB.
• Verify the non-overlap directly: assert no new transfer's ACCESS begins while the previous ACCESS is unfinished, that SETUP only follows a completed ACCESS, and cover that back-to-back streams run at exactly 1 / (2 + w) — so a resurrected pipeline assumption fails in regression, not at a boot deadline.