AMBA APB · Module 4

Single-Cycle Transfers

The fastest APB transfer — PREADY high in the first access cycle, so a transfer completes in two cycles (setup + access) with zero wait states.

Across Module 4 you have watched the access phase stretch under wait states and resolve on a single completion edge. This chapter looks at the opposite extreme: the fastest an APB transfer can go. A single-cycle transfer is a zero-wait-state access — the subordinate drives PREADY high in the very first access cycle, so the access completes immediately. But "single-cycle" names a single ACCESS cycle, not a single bus cycle: every APB transfer still costs a minimum of two PCLK cycles, one SETUP and one ACCESS, because APB always has a setup cycle. The single idea to carry: zero wait states is the floor, not pipelining — back-to-back single-cycle transfers are still two cycles each, adjacent and never overlapped.

1. What problem is being solved?

The problem is pinning down the fastest legal APB transfer and naming it precisely — so "single-cycle" never gets misread as "one clock."

Most subordinates on an APB bus are plain configuration registers that can answer the instant they are accessed. For them, inserting a wait state would be pure waste: the data is already there. APB lets such a subordinate finish in the minimum time by tying PREADY high, so the access completes on its first cycle. That gives the bus its best case:

PREADY high in the first access cycle — no wait states, the access completes at once.
Still one SETUP cycle first — the address and control are presented in SETUP with PENABLE low, before the access can begin.

So the floor is two PCLK cycles: one SETUP, one ACCESS. "Single-cycle" is the name engineers use for zero wait states — a single ACCESS cycle — and the value this chapter pins down is exactly that the minimum is two bus cycles, not one.

2. Why the previous model is not enough

You already understand wait states: the multi-cycle transfer where PREADY stays low and the access phase stretches. The natural next thought is "so the fast case must be a single clock cycle." That is the misread this chapter exists to prevent.

The danger is collapsing two distinct ideas into one number:

A single ACCESS cycle is not a single bus cycle. "Zero wait states" removes the extra access cycles, not the mandatory SETUP cycle. The transfer is still SETUP then ACCESS — two cycles.
PENABLE high is not, by itself, completion. In a single-cycle transfer PENABLE and PREADY happen to go high on the same cycle, so completion coincides with PENABLE rising — but the rule is still PSEL & PENABLE & PREADY. It is the conjunction that completes the transfer, not PENABLE alone.
Fast does not mean pipelined. A subordinate finishing in one access cycle does not let APB overlap the next transfer with this one. The next transfer's SETUP comes after this transfer's completion, never beside it.

So the model to add is not "the bus can do a transfer in one cycle." It is the precise floor — two cycles, one of them an unavoidable setup — and the discipline of keeping "single ACCESS cycle" and "single bus cycle" apart.

3. Mental model

The model: a single-cycle transfer is an express checkout — no queue at the counter, but you still walk up to it first.

Picture a shop with one express lane. The walk to the counter is SETUP: you present what you are doing (the address and control land, PSEL high, PENABLE low). The checkout itself is ACCESS. In the express lane the clerk is always ready — the stamp comes down the instant you arrive, because the subordinate ties PREADY high. There is no waiting at the counter. But you cannot skip the walk: APB always presents the access in SETUP before performing it in ACCESS. So the fastest trip is still two beats — walk, then stamp — and "single-cycle" means the stamp took one cycle, not the whole trip.

Three refinements make the model precise:

PREADY high in the first access cycle is the whole trick. A fast subordinate ties PREADY high, so the cycle PENABLE rises is also the cycle the access completes. There is never a wait cycle to hold the access.
SETUP is not optional. Even the fastest transfer spends one cycle in SETUP with PENABLE low. That cycle is what makes APB's access phase a clean, single-beat handshake — and it is why the floor is two cycles, not one.
Completion coincides with PENABLE here, but the rule is unchanged. In this best case PENABLE and PREADY are high together on one edge, so it looks like PENABLE completed the transfer. It did not — PSEL & PENABLE & PREADY did. The coincidence is exactly what makes a single-cycle waveform a trap for the rule.

Figure 1 — a single-cycle (zero-wait) APB transfer against PCLK. The phase bands read IDLE, SETUP, ACCESS·COMPLETE, then IDLE. PSEL goes high entering SETUP while PENABLE stays low and the address and write data become valid and are held. In the single ACCESS cycle PENABLE goes high and the subordinate already drives PREADY high in that same first access cycle, so PSEL, PENABLE, and PREADY are all high together — the dashed completion marker — and the access completes immediately. The annotation states the transfer is 2 cycles, 1 SETUP plus 1 ACCESS, the minimum, because APB always has a setup cycle, making this the fastest possible APB transfer.

4. Real SoC / hardware context

In RTL, a single-cycle transfer is what you get from the simplest possible subordinate: one that is always ready. It does not generate PREADY from a counter or a state bit — it ties the wire high and lets every access complete on its first access cycle.

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Snippet

// Fastest possible APB subordinate: always ready, zero wait states.
assign pready = 1'b1;   // ready in the FIRST access cycle of every transfer,
                        // so each access completes immediately — no wait states.
                        // This is the fastest an APB transfer can go.
                        // It does NOT make the transfer one cycle: every APB
                        // transfer is still SETUP + ACCESS = two PCLK cycles,
                        // because APB always presents the access in SETUP first.

Two facts fall out of this. First, because PREADY is held high, the access never has a wait cycle — the cycle PENABLE rises is the cycle the transfer completes, and this is true for every access to this subordinate. Second, the SETUP cycle is still there: the manager presents the address and control with PENABLE low for one cycle before driving PENABLE high, so even this trivial subordinate sees a two-cycle transfer. Tying PREADY high removes wait states; it cannot remove the setup cycle, which is part of APB's lifecycle, not the subordinate's choice.

5. Engineering tradeoff table

Making the fast case "one ACCESS cycle on top of a mandatory SETUP" is a deliberate design point. Each property trades something APB does not need for the simplicity it does.

Single-cycle property	What it gives up	What it buys	Why it is correct for APB
Mandatory SETUP cycle	A true one-cycle access	A clean, single-beat access handshake	The address must settle before the access is performed
`PREADY` tied high	Backpressure on this subordinate	The minimum-latency transfer, trivially	A register that is always ready needs no wait logic
Two-cycle floor (SETUP + ACCESS)	Peak throughput	Predictable, uniform transfer shape	A sparse control plane does not need higher rates
No overlap with the next transfer	Pipelined back-to-back accesses	Dead-simple, contention-free timing	APB chooses simplicity over bandwidth by design
Same lifecycle as a slow access	A separate fast path	One FSM handles fast and slow identically	Zero-wait is just the wait-count-equals-zero case

The throughline: the single-cycle transfer is not a special mode — it is the ordinary lifecycle with zero wait states. APB spends one mandatory setup cycle to keep the access phase a clean handshake, and in return the fastest and slowest transfers share one shape, one FSM, and one completion rule.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"A single-cycle transfer takes one PCLK cycle." No. It takes two — one SETUP and one ACCESS. "Single-cycle" means a single ACCESS cycle (zero wait states), not a single bus cycle. APB always has a setup cycle.
"Tying PREADY high makes the transfer one cycle." No. It removes wait states, so the access completes in its first access cycle — but the mandatory SETUP cycle remains, so the transfer is still two cycles.
"PENABLE high completed the single-cycle transfer." No. PENABLE and PREADY happen to go high on the same cycle here, so completion coincides with PENABLE — but the rule is still PSEL & PENABLE & PREADY, the conjunction, not PENABLE alone.
"Zero-wait, back-to-back transfers are pipelined." No. Each transfer is still SETUP + ACCESS = two cycles. The next transfer's SETUP follows this one's completion; the accesses are adjacent, never overlapped. Adjacent is not pipelined.
"A fast register needs the same wait-state logic as a slow one." No. An always-ready subordinate simply ties PREADY high — no counter, no state. The single-cycle case is the simplest subordinate, not a special one.
"Single-cycle is a different transfer type." No. It is the ordinary lifecycle with zero wait states — the same IDLE → SETUP → ACCESS shape and the same completion edge, just with nothing held in ACCESS.

7. Interview framing

This is a precision question: an interviewer asks "how many cycles is the fastest APB transfer?" and the answer separates someone who has internalised the lifecycle from someone who pattern-matches "single-cycle" to "one clock."

Lead with the floor: the fastest APB transfer is two PCLK cycles — one SETUP, one ACCESS — because APB always presents the access in SETUP before performing it. Then explain the name: "single-cycle" means a single ACCESS cycle, i.e. zero wait states, achieved when a fast subordinate ties PREADY high so the access completes on its first cycle. Add the depth point that completion still follows the full rule — PSEL & PENABLE & PREADY — and that in this case it merely coincides with PENABLE rising. Close with the trap most candidates miss: this is not pipelining — back-to-back zero-wait transfers are two cycles each, adjacent and never overlapped. Volunteering the SETUP-is-mandatory reason for the two-cycle floor is exactly what signals you understand the protocol, not just the buzzword.

8. Q&A

Figure 2 — a single-cycle (zero-wait) transfer stacked above a multi-cycle (one-wait) transfer, sharing the same clock shape. Top: a zero-wait transfer over two cycles — SETUP (PSEL high, PENABLE low), then one ACCESS cycle where PENABLE and PREADY are both high, completing on the dashed marker. Bottom: the same transfer with one wait state over three cycles — SETUP, then ACCESS spans two cycles, with PREADY held low for one access cycle (the wait, with PSEL, PENABLE and data held stable) before going high on the next, where completion lands. The annotation stresses the lifecycle shape IDLE-SETUP-ACCESS is identical in both; only the time spent in ACCESS differs — zero wait states versus one.

9. Practice

Count the floor. From memory, state how many PCLK cycles the fastest APB transfer takes and name each cycle. Explain why it cannot be fewer.
Write the fast subordinate. Write the one line of RTL an always-ready subordinate uses for PREADY, and say how many cycles each access then takes.
Name the coincidence. On a single-cycle transfer, mark the completion edge and explain why it is wrong to say "PENABLE high completed it" even though PENABLE is high there.
Spot the non-pipeline. Draw two back-to-back single-cycle transfers with no idle gap, label every cycle, and state the total cycle count — then explain why this is adjacent, not pipelined.
Compare the shapes. Draw a zero-wait transfer and a one-wait transfer one above the other and show that the only difference is the number of access cycles, not the lifecycle shape.

10. Key takeaways

A single-cycle transfer is a zero-wait-state access: the subordinate drives PREADY high in the first access cycle, so the access completes immediately.
"Single-cycle" means one ACCESS cycle, not one bus cycle. Every APB transfer is still a minimum of two PCLK cycles — one SETUP, one ACCESS — because APB always has a setup cycle.
A fast subordinate ties PREADY high — assign pready = 1'b1; — which removes wait states but never removes the mandatory SETUP cycle.
Completion still follows the full rule. PSEL & PENABLE & PREADY completes the transfer; here it merely coincides with PENABLE rising, so PENABLE high alone is not the completion condition.
This is not pipelining. Back-to-back zero-wait transfers are still two cycles each, adjacent and never overlapped — APB trades throughput for simplicity by design.
Single-cycle is just the zero-wait case of the ordinary lifecycle — same IDLE → SETUP → ACCESS shape, same FSM, same completion edge as a multi-cycle transfer; only the time spent in ACCESS differs.