AMBA APB · Module 4

The Setup Phase in Depth

The APB setup phase cycle by cycle — PSEL asserted with PENABLE low, address, control and write data presented and locked stable into the access phase.

The address phase told you SETUP exists and that it carries a stability contract. This chapter zooms all the way in to the single SETUP cycle, edge by edge against PCLK — what each signal does on the cycle SETUP begins, why PENABLE staying low is the entire point, and exactly when the presented values lock. The one idea to carry: SETUP only presents the access — it commits nothing — and the access it presents must hold stable from this cycle through ACCESS until the transfer completes. Everything in this chapter is that sentence at timing resolution.

1. What problem is being solved?

The problem is giving the subordinate one clean, settled cycle in which the access becomes visible — and nothing yet acts on it.

A subordinate cannot capture a write or drive read data the instant PADDR moves; it has to decode the address, decide whether it is the target, and ready its write enable or read mux. If presentation and commit landed on the same edge, decode would have to race the commit. APB carves out exactly one cycle up front where three things become simultaneously true:

The subordinate is selected. The relevant PSEL rises high so the targeted subordinate knows a transfer aimed at it has begun.
The access is presented. PADDR, PWRITE, and (for writes) PWDATA become valid together — the what of the transfer is now on the bus.
Nothing commits. PENABLE is held low, marking this cycle as preparation, not action.

That combination — PSEL high, PENABLE low, the access valid — is SETUP. Its only job is to hand the subordinate a settled view of the access one cycle before the access is performed.

Figure 1 — the SETUP cycle in detail against PCLK. Coming out of IDLE, PSEL rises high while PENABLE stays low, and PADDR, PWRITE, and PWDATA become valid together in the same cycle — the access is now presented. This single PSEL-high, PENABLE-low cycle is the subordinate's window to decode the address and prepare its response. SETUP lasts exactly one cycle; one cycle later PENABLE rises and the bus moves, unconditionally, into ACCESS where the access is actually performed.

2. Why the previous model is not enough

The address phase chapter gave you SETUP as a protocol phase — its place in the IDLE → SETUP → ACCESS lifecycle and the rule that presented values stay stable. That is correct, but it stops at the lifecycle level. Knowing SETUP is "the first phase" does not tell you what is true on the SETUP cycle edge by edge, nor exactly when its values lock — and timing bugs live in that gap.

Reasoning at lifecycle resolution leaves three concrete questions unanswered:

What is the signature of the SETUP cycle on a waveform? It is PSEL high and PENABLE low, simultaneously, for exactly one cycle. That combination is unique to SETUP — PENABLE is high in every ACCESS cycle and PSEL is low in IDLE. If you cannot point to it on a trace, you cannot tell SETUP from ACCESS.
When, precisely, do the presented values become valid — and when do they lock? They become valid in SETUP, on the cycle PSEL rises, and they must not change from that edge until completion. Stability is not a property of ACCESS that you remember to extend backward; it begins the cycle the access is presented.
What makes the SETUP→ACCESS move happen? Nothing conditional. SETUP is exactly one cycle and the move to ACCESS is unconditional — unlike the ACCESS→completion move, which waits on PREADY. Confusing the two is the root of most SETUP timing mistakes.

So the model to add is not another phase; it is the cycle-level reading of the one SETUP cycle: its signature, the instant its values lock, and the unconditional nature of its exit.

3. Mental model

The model: SETUP is showing your boarding pass and bag at the gate — it is checked, but you have not boarded, and you cannot swap the bag once it is on the belt.

You present everything at once — pass and bag (the access: PADDR, PWRITE, PWDATA). The agent needs one beat to read it (the decode window, PENABLE low — checked, not boarded). And the instant it is on the belt, you do not swap it; what you presented is what travels. SETUP is the presentation-and-freeze; ACCESS is the boarding.

Three refinements make the model precise:

One beat to read it. SETUP is exactly one cycle. The subordinate gets one settled cycle to decode PADDR and PWRITE; APB never lingers in SETUP and never skips it.
PENABLE low means "presented, not committed." While PENABLE is low the access is merely on the bus. PENABLE rising is the move from "checked" to "boarding" — from SETUP to ACCESS. It is what marks commit territory; nothing committed in SETUP itself.
The exit is unconditional. SETUP always advances to ACCESS after exactly one cycle. There is no handshake gating the SETUP→ACCESS edge; only the ACCESS→completion edge waits (on PREADY). SETUP is fixed; only ACCESS is elastic.

4. Real SoC / hardware context

In hardware the SETUP cycle is the one the manager (the APB bridge) drives to open a transfer, and the one the subordinate spends decoding. Both sides have complementary, deliberately cheap jobs in this single cycle.

On the manager side, entering SETUP means asserting the targeted PSEL, placing PADDR and PWRITE on the bus, placing PWDATA for a write — and holding PENABLE low. The bridge has just translated a fast-bus access into APB terms; SETUP is where it presents that access. Because the SETUP→ACCESS move is unconditional and one cycle, the manager logic is trivial: present this cycle, raise PENABLE next cycle.

On the subordinate side, SETUP is the cycle its address decoder works. A subordinate decodes PADDR against its register map to pick the target register and uses PWRITE to set its write enable or read mux — combinationally or registered off this cycle — so that by the time PENABLE rises in ACCESS it is ready to act or to drive PREADY. This is why the presented values must be stable: the decoder is staring at PADDR and PWRITE, and the result of that decode is only consumed when the access commits at completion. If the values moved between presentation and commit, the subordinate could select one register and act on another.

That is the load-bearing point of this whole chapter. The values presented in SETUP must be held constant from the SETUP edge through every ACCESS cycle — including wait states — until PREADY is sampled high. SETUP only presents; the commit happens far to the right, at completion. During a wait state the manager does nothing but keep holding the same values; the next access is presented only in a fresh SETUP after this one completes.

Figure 2 — the values presented in SETUP, locked into ACCESS. Top (legal): PADDR, PWRITE, and PWDATA are held as one unchanging value across SETUP and every ACCESS cycle, including a wait-state cycle where PREADY is low, right up to completion where PREADY is high; the subordinate decodes and captures the correct access, and only after completion are the values released. Bottom (illegal): the same signals are changed mid-transfer during an ACCESS cycle before completion (red), corrupting the access — the subordinate may decode or capture the wrong thing. The rule: what is presented in SETUP must stay stable through ACCESS until PREADY is high.

5. Engineering tradeoff table

The shape of the SETUP cycle is a set of deliberate choices. Each spends a little to buy the subordinate a clean, safe presentation window.

SETUP timing choice	What it gives up	What it buys	Why it is correct for APB
Exactly one SETUP cycle	A cycle of latency per transfer	A settled decode window before any commit	Latency is free for sparse control traffic
`PENABLE` low to mark "presented, not committed"	A separate "valid" strobe	One bit that distinguishes presentation from action	One marker reused on both sides; trivial logic
Values lock at the SETUP edge, not at ACCESS	Freedom to retime address/data late	A decode valid from presentation through commit	The decode result is consumed at completion
Unconditional SETUP→ACCESS exit	A way to stall in SETUP	One fixed entry into every transfer	Only ACCESS needs to be elastic; SETUP stays simple
Identical SETUP for reads and writes	Direction-specialised timing	One uniform presentation cycle	`PWRITE` carries direction; the phase shape need not

The throughline: SETUP spends one fixed cycle and one stability promise to present the access cleanly before anything is performed. By making the SETUP cycle's exit unconditional, APB pushes all the elasticity into ACCESS, keeping the presentation cycle trivial to drive and to verify.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

"The access is committed once it appears on the bus in SETUP." No. SETUP only presents the access. PENABLE is low precisely to say "not committed." The access is performed in ACCESS and commits only at completion, when PREADY is high.
"PSEL and PENABLE rise together at the start." No. In SETUP PSEL is high while PENABLE is low — that one-cycle gap is the entire signature of the phase. PENABLE rises one cycle later, to mark ACCESS.
"SETUP can stretch like ACCESS does." No. SETUP is always exactly one cycle and its exit is unconditional. Only ACCESS stretches, via PREADY. Nothing gates the SETUP→ACCESS edge.
"The presented values only need to be stable once ACCESS begins." No. They lock at the SETUP edge — the cycle they are presented — and must hold through ACCESS until completion. Stability begins in SETUP, not in ACCESS.
"During a wait state the manager can present the next access early." No. While PREADY is low the transfer is still in ACCESS and everything stays held. The next access is presented only in a fresh SETUP after this transfer completes.
"Reads and writes have different SETUP cycles." No. SETUP looks identical for both; PWRITE carries the direction and PWDATA is meaningful only for writes. The cycle's structure is uniform.

7. Interview framing

A favourite APB question is "what exactly happens in the SETUP cycle?" or "how do you tell SETUP from ACCESS on a waveform?" It probes whether you read APB at cycle resolution or only at lifecycle level.

Lead with the signature: SETUP is the one cycle where PSEL is high and PENABLE is low, simultaneously, and it lasts exactly one cycle. Then name what is presented — PADDR, PWRITE, and (for writes) PWDATA, all valid together — and stress that this is presentation, not commit; nothing lands in SETUP. Close with the two depth points that separate you: the presented values lock at the SETUP edge and hold through ACCESS until completion because the subordinate's decode is only consumed when the access commits; and the SETUP→ACCESS move is unconditional, unlike the ACCESS→completion move which waits on PREADY. Volunteering "SETUP is fixed at one cycle, only ACCESS is elastic" shows you understand which part of the transfer stretches and why.

8. Q&A

9. Practice

Point to SETUP. On a trace of a transfer with one wait state, mark the one cycle that is SETUP and state the exact PSEL/PENABLE condition you used to find it.
List what is presented. Name the three signals that become valid in the SETUP cycle and say which one is meaningful only for writes.
Find the lock point. State the precise cycle on which PADDR and PWDATA lock, and the precise cycle on which they are released, for a transfer with two wait states.
Spot the bug. A manager presents an address in SETUP, then changes PADDR during an ACCESS cycle in which PREADY was low. Name the rule it broke and what the subordinate might capture.
Contrast the exits. In one or two sentences, explain why the SETUP→ACCESS move is unconditional while the ACCESS→completion move waits on PREADY.

10. Key takeaways

The SETUP cycle's signature is PSEL high while PENABLE is low, simultaneously, for exactly one cycle — the unique way to identify SETUP on any APB waveform.
SETUP only presents the access; it commits nothing. PADDR, PWRITE, and (for writes) PWDATA become valid together, and the low PENABLE marks this cycle as preparation.
The presented values lock at the SETUP edge and hold unchanged through ACCESS until PREADY is high — stability begins when the access is presented, not when ACCESS starts.
SETUP is exactly one cycle and its exit is unconditional. Only ACCESS is elastic, via PREADY; nothing gates the SETUP→ACCESS edge and SETUP is never skipped.
PENABLE rising is the move into ACCESS, the boundary between "presented" and "performed" — completion is later still, where PSEL, PENABLE, and PREADY are all high.
The SETUP cycle is the subordinate's decode window, which is why the values must lock there: the decode is only consumed when the access commits, so a wobble between presentation and commit corrupts the transfer even when the lifecycle looks legal.