AMBA AXI · Module 6

AxADDR, AxLEN & AxSIZE

The three AXI signals that size every transfer — AxADDR (start address), AxLEN (beats − 1), and AxSIZE (bytes per beat = 2^AxSIZE) — and how they combine into total transfer size.

Module 6 dissects the AXI signals one group at a time, starting with the three that size every transfer: AxADDR (where it starts), AxLEN (how many beats), and AxSIZE (how many bytes per beat). The Ax prefix means both address channels — these are AWADDR/AWLEN/AWSIZE on writes and ARADDR/ARLEN/ARSIZE on reads, identical in meaning. Together they answer "start here, move this many beats of this width," which fixes the transfer's geometry and its total byte count. Getting their encodings exact — especially AxLEN's minus-one and AxSIZE's power-of-two — is foundational, and off-by-one or off-by-power errors here corrupt entire bursts.

1. Three Signals, One Geometry

A memory-mapped transfer is fully sized by three numbers on the address channel:

AxADDR — the start address (the address of the first beat).
AxSIZE — the bytes per beat, encoded as a power of two: bytes = 2^AxSIZE.
AxLEN — the number of beats minus one: beats = AxLEN + 1.

From these, the (aligned, INCR) total is beats × bytes_per_beat = (AxLEN+1) × 2^AxSIZE. They're declared once at the AR/AW handshake and govern the entire W or R burst that follows. The AxBURST type (next chapter) then says how the address steps between beats; these three say how big the transfer is.

Figure 1 — the three sizing signals. AxADDR is the start; AxSIZE is the width of each beat (2^AxSIZE bytes); AxLEN is the number of beats (AxLEN+1). Multiply width × beats for the total bytes. These fix the transfer's size at the address handshake, before any data moves.

2. AxADDR — The Start Address

AxADDR is the byte address where the transfer begins, as wide as the address bus (commonly 32, 40, or 64 bits). For a burst it is the address of the first beat only; the addresses of subsequent beats are derived from AxADDR, AxSIZE, and AxBURST — they are not sent on the bus. So a 16-beat INCR burst transmits one address and the subordinate computes the rest (Module 7 covers the per-beat address math).

AxADDR interacts with AxSIZE through alignment: an INCR burst is normally expected to start at an address aligned to AxSIZE (the beat width). An unaligned start is legal but has specific narrow-transfer/strobe consequences (Chapter 7.7). For now: AxADDR is the single start address; everything else about where each beat lands is computed from it.

3. AxSIZE — Bytes Per Beat

AxSIZE is a 3-bit field encoding the number of bytes transferred per beat as a power of two — bytes_per_beat = 2^AxSIZE:

`AxSIZE`	Bytes per beat
`3'b000`	1
`3'b001`	2
`3'b010`	4
`3'b011`	8
`3'b100`	16
`3'b101`	32
`3'b110`	64
`3'b111`	128

Two rules govern it. First, AxSIZE must not exceed the data-bus width: a 64-bit (8-byte) bus allows AxSIZE up to 3'b011 (8 bytes); requesting AxSIZE=3'b100 (16 bytes) on it is illegal. Second, AxSIZE selects which byte lanes carry data each beat — a beat of 2^AxSIZE bytes occupies that many lanes (positioned by the address). When AxSIZE equals the full bus width, every lane is used each beat (the common case); when it's smaller, the transfer is narrow (only some lanes active — Chapter 7.7).

4. AxLEN — Beats Minus One

AxLEN encodes the burst length as beats − 1, so the actual beat count is AxLEN + 1:

AxLEN = 0 → 1 beat (a single transfer)
AxLEN = 7 → 8 beats
AxLEN = 255 → 256 beats

The field is 8 bits in AXI4 (so 1–256 beats for INCR) and 4 bits in AXI3 (1–16 beats) — a key AXI3→AXI4 difference (Chapter 2.5). And the burst type constrains it: WRAP bursts are limited to lengths of 2, 4, 8, or 16 beats, while FIXED bursts are capped at 16 beats; only INCR uses the full 1–256 range.

The minus-one encoding is the perennial trap: AxLEN=15 is 16 beats, not 15. The W/R channel must deliver exactly AxLEN+1 beats with LAST on the final one (Chapters 4.4/5.3), so an off-by-one between the AxLEN you set and the beats you send malforms the burst.

5. Putting Them Together — Transfer Size

The three combine into the transfer's byte count. For an aligned INCR burst:

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Snippet

// Conceptual — the three signals define the transfer geometry.
localparam int BYTES_PER_BEAT = 1 << axsize;   // 2^AxSIZE
localparam int NUM_BEATS      = axlen + 1;      // AxLEN + 1
// total bytes (aligned INCR) = NUM_BEATS * BYTES_PER_BEAT
 
// Legality:
//   BYTES_PER_BEAT <= DATA_BUS_BYTES          (AxSIZE within the bus width)
//   AxBURST==WRAP → NUM_BEATS in {2,4,8,16}    (and addr aligned to the burst)

So a burst with AxSIZE=3'b011 (8 bytes/beat) and AxLEN=15 (16 beats) moves 16 × 8 = 128 bytes, starting at AxADDR. Change AxSIZE to 3'b010 (4 bytes/beat) and the same AxLEN moves 16 × 4 = 64 bytes in narrower beats. The product (AxLEN+1) × 2^AxSIZE is the number to carry in your head — and the two factors are independent levers: more beats or wider beats both increase the transfer.

Figure 2 — computing transfer size from the three signals. Decode AxSIZE to bytes-per-beat (2^AxSIZE), decode AxLEN to beats (AxLEN+1), and multiply for the total bytes — all starting at AxADDR. The two decoded factors are independent, so the same total can come from wide-short or narrow-long bursts.

axsize-beats — 4 beats × 4 bytes = 16 bytes

9 cycles

Figure 3 — the axsize-beats relationship. With AxSIZE=2 (4 bytes/beat) and AxLEN=3 (4 beats) starting at 0x100, the burst delivers four beats B0–B3 of 4 bytes each — 16 bytes total (0x100–0x10F for an INCR burst). AxSIZE sets each beat's width; AxLEN sets how many; their product is the transfer size.

6. AxSIZE vs the Data-Bus Width

The relationship between AxSIZE and the physical bus width is worth isolating because it's where two concepts meet:

AxSIZE == bus width — the normal, full-width case: every byte lane is used each beat, peak per-beat data movement.
AxSIZE < bus width — a narrow transfer: each beat moves fewer bytes than the bus can carry, so only some lanes are active (which lanes depends on the address). This is legal and useful (e.g., a small peripheral on a wide bus), but it under-utilizes the bus and has specific strobe/lane behavior — the subject of Chapter 7.7.
AxSIZE > bus width — illegal. A beat can't carry more bytes than the bus has lanes.

So AxSIZE is bounded above by the bus, and choosing it below the bus width is a deliberate (narrow) decision with bandwidth consequences. The interconnect may also down-size a transfer when crossing from a wide master to a narrow slave, changing the effective AxSIZE/beat-count on the far side.

Figure 4 — AxSIZE relative to the data-bus width. Equal to the bus: full-width beats, all lanes used (peak). Smaller than the bus: a narrow transfer, only some lanes active per beat (under-utilized, detailed in 7.7). Larger than the bus: illegal — a beat can't exceed the bus width.

7. Common Misconceptions

Myths to unlearn

"AxLEN is the number of beats." It's beats minus one: AxLEN=15 is 16 beats, AxLEN=0 is 1. The actual count is AxLEN+1.
"AxSIZE is the burst length." No — AxSIZE is bytes per beat (2^AxSIZE); AxLEN is how many beats. Two independent dimensions of the transfer.
"AxSIZE is a byte count you can set freely." It's a power-of-two encoding (0→1, 1→2, 2→4, …) and is bounded by the data-bus width. You can't set 3 bytes/beat, and you can't exceed the bus.
"Every beat's address is sent on the bus." Only AxADDR (the start) is sent; per-beat addresses are derived from AxADDR, AxSIZE, and AxBURST. One address, many beats.
"A wider AxSIZE always means more data." Total bytes = (AxLEN+1) × 2^AxSIZE — both factors matter. A wide-beat short burst and a narrow-beat long burst can move the same total; they differ in beat count and bus utilization.

8. Debugging Insight

🔍 Debugging insight — recompute the geometry from the three signals

When a transfer moves the wrong amount of data or lands at the wrong place, recompute its geometry straight from the address handshake:

Read AxSIZE → bytes per beat (2^AxSIZE). If this exceeds the data-bus width, the request is illegal and the subordinate/interconnect may mishandle it — a malformed transfer before any data.
Read AxLEN → beats (AxLEN+1). Then count the actual W/R beats: a mismatch with AxLEN+1 (or LAST on the wrong beat) is a length bug. Watch the minus-one: confusing AxLEN with the beat count is a top cause of off-by-one corruption.
Compute total bytes = (AxLEN+1) × 2^AxSIZE and compare to what the transfer should move. A factor-of-two discrepancy usually means a wrong AxSIZE (power-of-two slip); a count discrepancy means a wrong AxLEN.
Check AxADDR alignment to AxSIZE. An INCR burst starting unaligned to its beat width invokes narrow/unaligned behavior (7.7) and is a common source of "data landed shifted" bugs.

The discipline: the three signals fully determine the transfer's size and starting point, so most sizing bugs are visible by recomputing (AxLEN+1) × 2^AxSIZE from AxADDR and comparing to reality.

9. Verification Insight

✅ Verification insight — legality and the cross-product are the coverage

These three signals define a large legal space, and verification must both constrain to legal and cover the cross-product. Legality assertions/constraints: 2^AxSIZE ≤ DATA_BUS_BYTES (never request a beat wider than the bus); AxLEN within the version's range (≤ 15 for AXI3, ≤ 255 for AXI4) and within the burst-type limit (WRAP ∈ 16); and AxADDR alignment appropriate to the burst type. Coverage: the cross of AxSIZE × AxLEN — every legal beat width against single-beat, short, and max-length bursts — plus the corners (AxLEN=0, max AxLEN, AxSIZE = full-bus and AxSIZE < bus for narrow).

The scoreboard derives the expected transfer from the three signals: it computes NUM_BEATS = AxLEN+1 and BYTES_PER_BEAT = 2^AxSIZE, expects exactly that many beats ending in LAST, and (with AxBURST, next chapter) the per-beat addresses — so any DUT that miscounts beats or mis-sizes lanes mismatches immediately. The classic bugs caught here: off-by-one on AxLEN, a power-of-two slip on AxSIZE, and accepting an over-wide AxSIZE. Mechanics in Module 16.

10. Interview Questions

11. Summary

Three address-channel signals size every AXI transfer: AxADDR (the start address — the only address sent; per-beat addresses are derived), AxSIZE (bytes per beat as 2^AxSIZE, a 3-bit power-of-two field bounded by the data-bus width), and AxLEN (beats minus one, so AxLEN+1 beats — 8 bits/256-beat in AXI4, 4 bits/16-beat in AXI3). Their product, (AxLEN+1) × 2^AxSIZE, is the total byte count, and the two factors are independent levers on beat count and beat width.

The encodings are where bugs live: AxLEN's minus-one (15 means 16 beats), AxSIZE's power-of-two (and the must-not-exceed-the-bus rule), and AxADDR alignment to AxSIZE. Debug sizing problems by recomputing the geometry from the three signals and comparing to reality; verify by constraining to legal and covering the AxSIZE × AxLEN cross-product. With how big settled, the next chapter covers how the address steps — AxBURST (FIXED/INCR/WRAP).

12. What Comes Next

You can size any transfer; next, how its address advances:

6.2 — AxBURST (coming next) — the burst-type encoding (FIXED / INCR / WRAP) and what each is for.
6.3 — AxID (coming soon) — transaction-ID semantics and how IDs route and order traffic.

Previous: 5.6 — Read Transaction Waveforms. For the broader protocol catalog, see the AMBA family overview doc.