AMBA AXI · Module 6

AxBURST

The AXI burst-type signal — FIXED, INCR, and WRAP — what each does to the address between beats, and the use case for each (FIFO ports, memory, cache-line fills).

The last chapter sized a transfer; AxBURST says how its address steps from beat to beat. It's a 2-bit field with three types — FIXED, INCR, and WRAP — and each maps to a distinct real use: FIXED for a single peripheral/FIFO port, INCR for sequential memory (the workhorse), and WRAP for cache-line fills. Because only AxADDR (the start) is sent on the bus, AxBURST (with AxSIZE) is what tells the subordinate how to compute every later beat's address. This chapter explains the encoding and the behavior of each type; the exact per-beat address arithmetic (and the 4KB-boundary rule) is Module 7.

1. AxBURST — How the Address Steps

AxBURST is a 2-bit field on the address channel (AWBURST/ARBURST):

`AxBURST`	Type	Address between beats
`2'b00`	FIXED	Stays the same every beat
`2'b01`	INCR	Increments by the beat size (`2^AxSIZE`)
`2'b10`	WRAP	Increments, then wraps at an aligned boundary
`2'b11`	reserved	—

AxBURST works with AxSIZE and AxLEN: AxSIZE gives the step (bytes per beat), AxLEN gives how many beats, and AxBURST gives the pattern of stepping. From AxADDR plus these three, the subordinate derives every beat's address — the manager never sends them individually.

Figure 1 — the three burst types. FIXED keeps the same address every beat (one location, repeatedly). INCR increments the address by the beat size each beat (sequential). WRAP increments but wraps back at an aligned boundary (cache-line fills). AxBURST sets the pattern; AxSIZE sets the step; AxLEN sets the count.

2. FIXED — Same Address Every Beat

A FIXED burst keeps AxADDR constant for all beats — every beat targets the same address. It's for accessing a single location repeatedly: most often a peripheral's data port / FIFO, where you push or pull multiple beats to one register address and the device's internal pointer advances, not the bus address.

FIXED bursts are limited to 16 beats maximum. They're the right choice when the target is a port, not a memory range — e.g., draining a UART RX FIFO or streaming to a peripheral's TX register. Using INCR there would walk the address off the single port into neighboring registers; FIXED holds it in place.

3. INCR — Incrementing (the Workhorse)

An INCR burst increments the address by the beat size (2^AxSIZE) on each beat, so successive beats target consecutive locations. It's the overwhelmingly common type — sequential reads/writes to memory: instruction fetches, DMA block transfers, cache line writes, frame buffers. INCR supports the full burst-length range (1–256 beats in AXI4), so it's how large, contiguous transfers move efficiently.

For AxADDR=A and beat size S, the beat addresses are A, A+S, A+2S, A+3S, …. There's no wrap and no fixed cap (beyond 256), and the start is normally aligned to S. INCR is what you reach for unless you specifically need FIXED's single-port behavior or WRAP's cache-line semantics.

4. WRAP — Increment, Then Wrap (Cache Lines)

A WRAP burst increments like INCR but wraps back to an aligned lower boundary when it reaches the top of an aligned region. Its purpose is cache-line fills with critical-word-first: a CPU that misses on a word in the middle of a cache line can request that word first (low latency to the data it needs), and the burst wraps around to fetch the rest of the line.

WRAP has strict rules: the length must be 2, 4, 8, or 16 beats (not arbitrary), and AxADDR must be aligned to the beat size. The wrap boundary is the total burst size (beats × 2^AxSIZE), aligned. So a 4-beat WRAP of 4-byte beats starting at 0x34 covers the 16-byte region 0x30–0x3F: it goes 0x34, 0x38, 0x3C, then wraps to 0x30. The critical word (0x34) came first; the line filled completely.

5. Address Progression Compared

The three types side by side make the difference concrete. Take AxADDR=0x34, AxSIZE=2 (4 bytes/beat), AxLEN=3 (4 beats):

Figure 2 — beat addresses for each burst type (AxADDR=0x34, 4-byte beats, 4 beats). FIXED: 0x34 every beat. INCR: 0x34, 0x38, 0x3C, 0x40 (straight up). WRAP: 0x34, 0x38, 0x3C, then wraps to 0x30 (filling the 16-byte line 0x30–0x3F, critical word 0x34 first). Same start and size, three different address sequences.

On the address channel itself, only AxADDR and AxBURST are driven; the beat addresses are derived as the data beats transfer:

axburst-types — INCR address progression (derived)

9 cycles

Figure 3 — axburst-types on the bus (INCR example). The address handshake carries AxADDR=0x34, AxBURST=INCR, AxSIZE=2 (4-byte beats); only that one address is sent. As the four data beats transfer, the effective beat address (derived, not bussed) steps 0x34, 0x38, 0x3C, 0x40. For WRAP it would wrap to 0x30 on the last beat; for FIXED it would stay 0x34.

6. Choosing a Burst Type

Each type maps to a use, and the choice follows the target's nature:

Figure 4 — burst type by use case. A single port/FIFO (one address, many beats) → FIXED. Sequential memory (consecutive addresses) → INCR, the default for almost all memory traffic. A cache-line fill needing critical-word-first → WRAP. The target's nature picks the burst type.

7. Common Misconceptions

Myths to unlearn

"FIXED means the data is the same." No — FIXED means the address is the same every beat; the data still differs per beat. It targets one location (a port/FIFO) repeatedly.
"WRAP can be any length." WRAP lengths must be 2, 4, 8, or 16 beats, with AxADDR aligned to the beat size. Arbitrary lengths are INCR-only.
"INCR and WRAP differ only by a wrap at the end." They also differ in constraints: INCR is 1–256 beats and starts at the critical word with no wrap; WRAP is restricted (2/4/8/16, aligned) precisely because it fills an aligned cache line.
"The subordinate is told every beat's address." Only AxADDR (the start) is sent. The subordinate derives the rest from AxADDR + AxSIZE + AxBURST. That's why AxBURST exists.
"Use INCR for everything." INCR is the default for memory, but FIXED is correct for single-port/FIFO targets (INCR would walk off the port) and WRAP is correct for critical-word-first cache fills. Match the type to the target.

8. Debugging Insight

🔍 Debugging insight — derive the beat addresses from AxBURST and check where data landed

When write data lands at the wrong addresses (or a read returns the wrong locations), recompute the beat addresses from the address handshake:

Read AxBURST, AxADDR, AxSIZE, AxLEN and derive the expected per-beat addresses: FIXED → all AxADDR; INCR → AxADDR + n·2^AxSIZE; WRAP → INCR with a wrap at the aligned boundary.
FIXED vs INCR mix-up? A common bug: a FIFO/port accessed with INCR walks across neighboring registers (data scattered into wrong locations), or a memory range accessed with FIXED stacks all beats onto one address (only the last beat's data survives). The symptom — "data spread out" vs "data collapsed to one location" — tells you which way the burst type is wrong.
WRAP legality. Check the length is 2/4/8/16 and AxADDR is aligned; an illegal WRAP (odd length, unaligned) is malformed and subordinates may handle it inconsistently.
WRAP boundary. If a cache fill lands wrong, verify the wrap boundary is beats × 2^AxSIZE aligned — a wrong boundary scatters the line.

The discipline: AxBURST + AxADDR + AxSIZE fully determine where each beat goes, so most "wrong address" bugs are visible by deriving the sequence and comparing to where data actually landed.

9. Verification Insight

✅ Verification insight — cover all three types and assert WRAP legality

The burst type multiplies the address space the scoreboard must model, so verification covers all three and checks the derived addresses. The scoreboard computes the expected per-beat address sequence from AxBURST/AxADDR/AxSIZE/AxLEN and checks data landed at exactly those locations — catching FIXED/INCR/WRAP implementation bugs (e.g., a slave that treats FIXED as INCR). Legality assertions: WRAP length ∈ 16 and AxADDR aligned to the beat size; FIXED length ≤ 16; AxBURST != 2'b11 (reserved). Coverage wants each type crossed with sizes and (legal) lengths, plus the corners: FIXED to a port, INCR at max length, WRAP at each legal length with the critical word at different offsets so the wrap point varies.

WRAP deserves special attention because its address math is the trickiest — verify the wrap occurs at the correct aligned boundary and that the critical-word-first ordering is honored. The interconnect's burst handling (and any width down-sizing that converts a wide burst into a different shape) is another fertile area. Mechanics in Module 16, with the address math itself in Module 7.

10. Interview Questions

11. Summary

AxBURST is the 2-bit field that says how the address steps between beats, working with AxSIZE (the step) and AxLEN (the count) so the subordinate can derive every beat's address from the single AxADDR. FIXED (00) holds the address constant — for single ports/FIFOs (≤16 beats); INCR (01) increments by 2^AxSIZE — the workhorse for sequential memory (1–256 beats); WRAP (10) increments then wraps at an aligned boundary — for critical-word-first cache-line fills (length 2/4/8/16, aligned start). 2'b11 is reserved.

The choice follows the target: a port wants FIXED, memory wants INCR, a cache fill wants WRAP — and using the wrong type produces telltale symptoms (FIXED-as-INCR scatters data across registers; INCR-as-FIXED collapses it to one address). Debug "wrong address" bugs by deriving the per-beat sequence from AxBURST/AxADDR/AxSIZE and comparing to where data landed; verify all three types with address-sequence checks and WRAP legality assertions. Next: AxID, the transaction identifier that routes and orders traffic.

12. What Comes Next

You know how the address steps; next, how transactions are identified and ordered:

6.3 — AxID (coming next) — transaction-ID semantics and how IDs route and order traffic.
6.4 — AxLOCK & AxCACHE (coming soon) — the lock (exclusive) and cache/memory-attribute encodings.

Previous: 6.1 — AxADDR, AxLEN & AxSIZE. For the broader protocol catalog, see the AMBA family overview doc.