AMBA AXI · Module 15

Reusable AXI RTL Templates

Assemble the Module 15 building blocks into a reusable, parameterised AXI RTL library — the primitive set (skid, FIFO, register bank, FSMs, adapters), the parameterisation and naming conventions that make blocks composable, how to build subsystems by wiring primitives, and the conventions that keep a library correct-by-construction.

This chapter closes Module 15 by stepping back from individual blocks to the library. Across the module we built a simple AXI4-Lite slave, a parameterised register bank, write and read FSMs, the skid buffer, ready/valid pipelining, and FIFOs. Individually they're useful; assembled into a consistent, parameterised, drop-in library they become the foundation every AXI design reuses. The leverage isn't any one block — it's the conventions that let blocks compose without rework: a uniform VALID/READY interface, consistent parameter and signal naming, sensible defaults, and a clear menu of when to reach for which primitive. This chapter catalogs the primitive set, states the parameterisation and naming conventions that make them composable, shows how to build subsystems by wiring primitives, and lists the conventions that keep a library correct-by-construction.

1. The Primitive Set

A practical AXI RTL library is a small, orthogonal set of primitives — each does one thing, all share the same handshake interface, and larger blocks are compositions of them.

Figure 1 — the reusable AXI primitive set. Flow-control primitives (skid buffer, FIFO, ready/valid pipeline stage) register and buffer handshakes; protocol engines (write FSM, read FSM) sequence bursts; storage (register bank) holds memory-mapped state; adapters (width, protocol, clock-domain) bridge mismatches. Every block presents the same VALID/READY interface, so they compose freely.

The menu — which primitive solves which problem — is the library's real interface:

Need	Primitive	From
Register a handshake for timing	Skid buffer	15.5
Decouple producer/consumer rates, absorb bursts	FIFO (sync)	15.7
Cross a clock domain	FIFO (async)	15.7 / 14.2
Multi-stage timing pipeline	Ready/valid pipeline (skid stages)	15.6
Sequence a write burst	Write FSM	15.3
Sequence a read burst	Read FSM	15.4
Memory-mapped control/status	Register bank	15.2
Minimal control slave	AXI4-Lite slave	15.1

2. Parameterisation Conventions

Composability comes from uniform parameters. Every block in the library is parameterised on the same axes, with the same names, so instances line up and width/ID mismatches are caught at elaboration:

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Snippet

// Standard parameter set, shared by every AXI block in the library
parameter int ADDR_W  = 32,   // address width
parameter int DATA_W  = 64,   // data width (bytes = DATA_W/8 → WSTRB width)
parameter int ID_W    = 4,    // transaction ID width
parameter int USER_W  = 0,    // sideband width (0 = none)
parameter int LEN_W   = 8,    // AWLEN/ARLEN width (8 = AXI4 up to 256 beats)
parameter int DEPTH   = 2     // buffer depth (2 = skid; larger = FIFO)

The conventions that make this work: derive, don't duplicate (STRB_W = DATA_W/8 is computed, never passed separately, so it can't disagree); safe defaults (a block with default DEPTH=2 is a skid buffer; bump it for a FIFO); width-agnostic logic (loops and slices use the parameters, never hardcoded 32/8); and elaboration-time assertions (initial assert (DATA_W inside {32,64,128,...})) to reject illegal configurations at build time rather than failing in simulation.

Figure 2 — parameterisation as the composability contract. A shared parameter set (ADDR_W, DATA_W, ID_W, USER_W, LEN_W, DEPTH) is threaded identically through every block; derived values (STRB_W = DATA_W/8) are computed not passed; defaults make the common case trivial; elaboration-time assertions reject illegal widths. Identical parameters across blocks mean instances connect without glue and mismatches fail at build time.

3. Naming and Interface Conventions

The second half of composability is naming. If every block names its handshake ports the same way, wiring is mechanical and review is fast:

Direction prefixes: s_ for the subordinate (slave) side that receives, m_ for the manager (master) side that drives — so a block's input channel is s_* and its output channel is m_*, and connecting m_* of one block to s_* of the next is a one-to-one name match.
Channel suffixes: the AXI channel signal names verbatim (awvalid, awready, awaddr, wdata, wstrb, wlast, bresp, …) so a full AXI port is a recognizable, complete set.
Active-low reset aresetn, single clock aclk per domain, named consistently.
One handshake rule, everywhere: *VALID and payload driven independently of *READY; payload stable until accepted; exactly the contract every primitive already obeys.

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Snippet

// A library block's AXI write-channel ports — same names in every block
input  logic [ID_W-1:0]   s_awid,
input  logic [ADDR_W-1:0] s_awaddr,
input  logic [LEN_W-1:0]  s_awlen,
input  logic              s_awvalid,
output logic              s_awready,
// ... m_aw* on the output side, identical suffixes

Figure 3 — naming makes wiring mechanical. Each block exposes a subordinate side (s_*) that receives and a manager side (m_*) that drives, using verbatim AXI channel suffixes. Connecting one block's m_* port to the next block's s_* port is a one-to-one name match, so chaining primitives needs no translation glue and connection errors are visually obvious.

4. Building Subsystems by Composition

With a uniform interface and naming, subsystems are wiring diagrams. A registered, rate-decoupled AXI4-Lite peripheral, for example, is just primitives chained: a skid buffer at the port (timing), the Lite slave / register bank (function), and optionally a FIFO where buffering is needed — each m_* to the next s_*. Larger blocks (an interconnect port, a data mover, a width converter) are the same idea at larger scale.

Figure 4 — a subsystem as composed primitives. An AXI port skid buffer (timing closure) feeds a register bank (function); a data path adds a FIFO (rate decoupling) ahead of a width adapter; clock crossings use an async FIFO. Each connection is m_* → s_*. The subsystem inherits correctness from its primitives — each already obeys the handshake contract — so integration is wiring, not redesign.

5. Common Misconceptions

Myths to unlearn

"A reusable block is just code you copy-paste." Reuse is about conventions, not copying. A block is reusable only if its interface, parameters, and naming match the rest of the library so it composes without glue. Copy-paste without convention creates divergent, incompatible variants.
"Parameterise everything for maximum flexibility." Over-parameterisation (a knob for every conceivable variation) makes blocks hard to use and verify. Parameterise the standard axes (widths, ID, depth) with safe defaults; resist exotic knobs that explode the configuration space.
"Derived widths should be parameters too, for control." No — anything derivable (STRB_W = DATA_W/8) must be computed, never passed, so it can't disagree with its source. Passing it separately invites mismatch bugs.
"Composing correct blocks always yields a correct system." Each block is locally correct, but composition can still introduce system-level issues — deadlock from a FIFO in a dependency loop (15.7), ordering across reconvergent paths, or insufficient outstanding depth. Composition reduces risk but doesn't eliminate system-level analysis.
"Naming is cosmetic." Consistent s_/m_ + verbatim channel suffixes turn integration into a one-to-one name match and make connection errors visually obvious. Inconsistent naming is a leading cause of integration bugs and slow reviews.
"A library doesn't need its own verification." Each primitive must be verified once, thoroughly (the skid/FIFO/FSM tests from this module) so that every instance is trusted; that up-front cost is exactly what makes downstream reuse safe and fast.

6. Debugging Insight

🔍 Debugging insight — integration bugs trace to interface, parameter, or composition mismatches

When a composed AXI subsystem misbehaves, the fault is usually at the seams, not inside a (already-verified) primitive:

Signals don't connect / widths mismatch at elaboration. A parameter wasn't threaded consistently — one block instanced with DATA_W=32, the next default 64. The elaboration-time width assertions should catch this; if they don't exist, add them.
Handshake stalls at a block boundary. A m_*/s_* pairing is crossed or a READY/VALID left unconnected (floating). Check the one-to-one name match at the seam; an unconnected READY reads as a stuck handshake.
Data corruption across a boundary. A derived width (e.g. WSTRB) disagrees because it was passed instead of computed, or an adapter is mis-parameterised. Verify derived values are computed from the shared source.
System deadlock despite correct primitives. A composition-level dependency loop (e.g. response FIFO in a cycle) — not a block bug. Trace the cross-channel dependencies (15.7's deadlock analysis).
Timing fails at integration though each block closed. The composition created a long combinational path across blocks that each individually met timing (e.g. two bare-register stages back to back, or an unregistered adapter between skids). Insert a skid at the offending seam.
One instance behaves differently. It was configured with a non-standard parameter or an exotic knob; check its instantiation against the library defaults.

The recurring theme: verified primitives + buggy seams. Because each block is trusted, debugging a subsystem is mostly checking the connections, parameters, and composition-level properties — which is exactly the payoff of a convention-driven library.

7. Verification Insight

✅ Verification insight — verify primitives once, then verify composition and configuration

A library's verification strategy is two-tier, and it's what makes reuse trustworthy. Tier 1 — per-primitive, thorough, once: each block gets the exhaustive treatment from its own chapter (skid: throughput-through-stall + formal conservation; FIFO: overflow/underflow + conservation + CDC; FSMs: burst-length sweep + stall injection + protocol assertions; register bank: model-driven map sweep). Crucially, verify each primitive across its parameter range (representative DATA_W/ID_W/DEPTH values), since the library will instantiate many configurations — a block is only "verified" for the configs you actually checked, so cover the corners (min/max width, depth=2, depth large). Tier 2 — composition and configuration: with primitives trusted, integration verification focuses on (a) seam correctness — assertions that every m_*→s_* connection obeys the handshake at the boundary, and elaboration assertions that parameters match; (b) composition-level properties — end-to-end data conservation/ordering through the subsystem, and the system-level deadlock/outstanding-depth analysis that primitive tests can't see; (c) configuration coverage — that each shipped configuration of the library has been elaborated and smoke-tested. A standard AXI protocol checker / VIP attached at subsystem boundaries provides the seam assertions almost for free (the bridge to Module 16). The payoff: because primitives are proven once, subsystem verification is small and targeted — seams, composition properties, and config coverage — rather than re-deriving each block's behavior. This two-tier model is why a well-built library accelerates every downstream project: the expensive proof is amortized, and integration is reduced to checking connections and emergent properties. It also sets up Module 16, where we build exactly the assertion/monitor/scoreboard/coverage machinery that verifies both the primitives and the seams.

8. Interview Questions

9. Summary

A reusable AXI RTL library is less about any single block than about the conventions that make blocks compose. The primitive set is small and orthogonal — flow control (skid buffer, FIFO, pipeline stage), protocol engines (write FSM, read FSM), storage (register bank), and adapters (width/protocol/CDC) — and a clear menu maps each design need to a primitive. Parameterisation conventions thread the same axes (ADDR_W, DATA_W, ID_W, USER_W, LEN_W, DEPTH) through every block, derive dependent values (STRB_W = DATA_W/8) instead of passing them, supply safe defaults, and assert legal configurations at elaboration. Naming conventions (s_/m_ direction prefixes + verbatim AXI channel suffixes) turn integration into a one-to-one name match, making wiring mechanical and connection errors obvious.

With a uniform interface and naming, subsystems are wiring diagrams — a port skid for timing, a register bank or FSM for function, a FIFO for rate decoupling, an async FIFO at clock crossings, each m_* to the next s_* — and they inherit correctness from their primitives. The discipline that keeps a library correct-by-construction: verify each primitive once, thoroughly, across its parameter range, then focus integration verification on seams, composition-level properties (deadlock, ordering, depth, timing), and configuration coverage — because local correctness is necessary but not sufficient for system correctness. This completes Module 15 (Building / Hands-On): from a single Lite slave to a composable library. Next, Module 16 builds the verification machinery — the checker mindset, SVA assertions, monitors, scoreboards, and coverage — that proves both the primitives and the systems built from them.

10. What Comes Next

You've built and packaged the RTL; Module 16 turns to proving it correct:

16.1 — The Protocol-Checker Mindset (coming next) — how to think about what could violate the AXI spec, the foundation for the assertions, monitors, scoreboards, and coverage that verify everything you've built.

Previous: 15.7 — FIFO-Based Buffering. Related: 15.1 — A Simple AXI4-Lite Slave and 15.5 — The Skid Buffer for the primitives this library assembles, and 10.5 — AXI4-Lite Verification Checklist for the per-block verification the library depends on.