AMBA AXI · Module 15

The Skid Buffer

Build the workhorse of pipelined AXI — a two-entry skid buffer that fully registers a VALID/READY handshake for timing closure while sustaining one-beat-per-cycle throughput. Why a single register stalls, how the skid (overflow) register absorbs the bubble, and the FSM that runs it.

Every AXI channel is a VALID/READY handshake, and at speed those handshakes must be registered on both sides to close timing — an unregistered path lets the consumer's READY ripple combinationally back to the producer, creating a long, often critical, path across a chip. But naively registering the handshake either breaks throughput (you drop to one beat every two cycles) or breaks the protocol (you lose data when the downstream stalls). The skid buffer is the standard solution: a small, two-entry buffer that registers both VALID and READY, breaks the combinational path in both directions, and still sustains full one-beat-per-cycle throughput. It's the most reused piece of AXI RTL there is — in interconnect ports, FSM outputs, FIFO front-ends, and pipeline stages. This chapter builds it and explains exactly why the "skid" (overflow) register is necessary.

1. The Problem: Registering a Handshake Naively

You want to insert a pipeline register in an AXI channel so neither side sees a combinational path through the other. The naive options both fail:

Register only the data + VALID (a "pipe" stage), pass READY straight through combinationally. This breaks the forward path but leaves READY rippling backward — timing isn't fully closed.
Register READY too, with a single data register. Now both directions are registered, but there's a hazard: in the cycle the downstream asserts READY after a stall, the upstream — which only just saw READY go high (it's registered, so one cycle late) — may have already placed a new beat on the bus. With only one register, you have nowhere to put the beat that's "in flight" when READY toggles. You either drop it (data loss) or you must have held off accepting it, costing a bubble every time READY deasserts — half throughput.

The fix is a second register — the skid or overflow register — to catch exactly that one in-flight beat. Two registers are both necessary and sufficient for a fully-registered, full-throughput handshake.

Figure 1 — why one register isn't enough. With registered READY, the upstream learns of a stall one cycle late, so a beat can already be in flight when the buffer fills. A single data register has nowhere to hold it — forcing either data loss or a one-cycle bubble per stall (half throughput). A second 'skid' register catches that in-flight beat, restoring full throughput.

2. The Two-Entry Structure

A skid buffer holds up to two beats: a main register that feeds the output, and a skid register that captures the overflow beat that arrives in the cycle the buffer becomes full. Upstream READY is asserted whenever the skid register is empty (i.e. there's room for one more in-flight beat), so the upstream never sees a combinational READY and is never starved while space exists.

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Snippet

module skid_buffer #(parameter int W = 32) (
  input  logic         clk, rstn,
  // upstream (sink)
  input  logic [W-1:0] s_data,
  input  logic         s_valid,
  output logic         s_ready,
  // downstream (source)
  output logic [W-1:0] m_data,
  output logic         m_valid,
  input  logic         m_ready
);
  logic [W-1:0] skid_data;
  logic         skid_valid;
 
  // Accept upstream while we have room for the overflow beat
  assign s_ready = !skid_valid;
 
  always_ff @(posedge clk) begin
    if (!rstn) begin
      m_valid <= 1'b0; skid_valid <= 1'b0;
    end else begin
      if (s_ready) begin
        // room: capture incoming beat into skid if output is busy,
        // else straight into the main register
        if (m_valid && !m_ready) begin
          // output stalled and we just took a beat → it skids
          if (s_valid) begin skid_data <= s_data; skid_valid <= 1'b1; end
        end else begin
          // output free (or being consumed): load main directly
          m_data  <= s_valid ? s_data : m_data;
          m_valid <= s_valid ? 1'b1 : (m_ready ? 1'b0 : m_valid);
        end
      end
      // when output is consumed and a skid beat waits, promote it
      if (m_valid && m_ready) begin
        if (skid_valid) begin
          m_data <= skid_data; m_valid <= 1'b1; skid_valid <= 1'b0;
        end else if (!s_ready || !s_valid) begin
          m_valid <= 1'b0;
        end
      end
    end
  end
endmodule

(The exact coding varies — many equivalent forms exist — but the invariant is the same: s_ready = !skid_valid, the skid register catches the overflow beat, and a consumed output promotes the skid beat.)

Figure 2 — the two-entry skid buffer datapath. The main register drives the output (m_data/m_valid); the skid register holds one overflow beat. Upstream is accepted (s_ready) whenever the skid is empty. When the output is consumed (m_valid && m_ready), a waiting skid beat is promoted into the main register. Two slots are exactly enough to fully register both directions without bubbles.

3. The State Machine

The skid buffer's occupancy is a tiny FSM over three states by fill level: EMPTY (no beat; s_ready=1, m_valid=0), ONE (main holds a beat; s_ready=1, m_valid=1 — still room in skid), and FULL (main + skid both hold beats; s_ready=0, m_valid=1). Throughput is full because in the common streaming case the buffer sits in ONE, accepting and emitting a beat every cycle.

Figure 3 — the skid buffer occupancy FSM. EMPTY accepts a beat into main (→ ONE). ONE emits when downstream is ready and can simultaneously accept a new beat (self-loop = steady-state streaming); if downstream stalls while a new beat arrives, it fills the skid (→ FULL). FULL deasserts s_ready; when downstream consumes, the skid beat promotes to main (→ ONE). The steady state is ONE with a self-loop — one in, one out, every cycle.

4. The Timing: Full Throughput Through a Stall

The waveform shows the payoff: a stream of beats flows one-per-cycle; when the downstream drops m_ready for a cycle, the skid register catches the in-flight beat so no data is lost and no upstream bubble is created — when m_ready returns, the skid beat is emitted and streaming resumes at full rate.

Skid buffer absorbing a one-cycle stall

9 cycles

Figure 4 — full throughput across a downstream stall. Beats stream in (s_valid/s_ready) and out (m_valid/m_ready) one per cycle. At cycle 4 the downstream drops m_ready; the buffer goes FULL and the in-flight beat lands in the skid register — s_ready deasserts for exactly one cycle to hold the upstream. When m_ready returns (cycle 5), the skid beat is emitted and the pipeline resumes at one beat per cycle. No beat is dropped; the only backpressure is the single registered s_ready pulse.

5. Common Misconceptions

Myths to unlearn

"A single pipeline register is enough to register a handshake." It registers the forward path but either leaves READY combinational (timing not closed) or, if READY is registered too, loses a beat / costs a bubble. You need two entries to fully register both directions at full throughput.
"A skid buffer is just a 2-deep FIFO." Functionally similar, but a skid buffer is specifically the minimum structure (two registers) to break the combinational VALID/READY path in both directions while sustaining one-beat-per-cycle. FIFOs are sized for buffering/rate-matching; a skid buffer is sized for timing.
"The skid buffer adds latency you can't avoid." It adds one cycle of latency (the register stage) — that's the cost of registering the path. Throughput is unaffected; only latency increases by a cycle, which is exactly what pipelining trades.
"s_ready can be combinational off m_ready." That's the whole bug it exists to prevent — s_ready must be registered (here, !skid_valid), with no combinational path from m_ready. Otherwise you've reintroduced the long path.
"It only matters for high-frequency designs." Any time an FSM or interconnect port drives an AXI handshake, an unregistered READY/VALID can become the critical path or violate the no-VALID-waits-on-READY rule. Skid buffers are routine even at modest frequencies.
"You can drop m_valid while a beat is unconsumed." Once m_valid is high it must stay high with stable m_data until m_ready; the skid logic preserves this — promoting the skid beat keeps m_valid asserted across the transition.

6. Debugging Insight

🔍 Debugging insight — skid-buffer bugs show up as lost beats, bubbles, or reintroduced long paths

When a skid buffer is wrong, the symptom is specific:

Data lost under backpressure. The skid register isn't capturing the in-flight beat — usually s_ready is deasserted too late (combinational off the wrong term) or the overflow path doesn't write the skid register. Confirm s_ready = !skid_valid and that an incoming beat during a stall lands in skid.
Throughput drops to one beat every two cycles. The buffer is bubbling — likely s_ready deasserts whenever m_valid is high (treating ONE as full), instead of only when the skid is occupied. The steady state must be the ONE self-loop, not EMPTY↔ONE.
Timing still fails on the READY path. s_ready (or m_valid) has a combinational path to the far side — the register wasn't actually inserted. Check that both s_ready and m_valid are flops, with no combinational m_ready → s_ready term.
m_data changes while m_valid is high and m_ready low. Payload-stability violation — the main register is being overwritten during a stall. It must only update when the output is consumed or empty.
Buffer deadlocks (never drains). The promote logic (skid→main on consume) is missing or mis-conditioned, so a FULL buffer never returns to ONE. Verify the consume-and-promote step.

The two signature bugs are lost-beat (skid not catching) and half-throughput (s_ready too conservative) — both are checked directly by the full-throughput-through-a-stall test in §7.

7. Verification Insight

✅ Verification insight — the throughput-through-stall test plus formal handshake properties

A skid buffer is small enough to verify decisively. Always-on assertions: payload stability (m_data constant while m_valid && !m_ready); m_valid never drops with a beat pending (only on consume); s_ready and m_valid are registered (no combinational m_ready → s_ready path — checkable structurally or with a formal "X on m_ready doesn't propagate combinationally to s_ready"); and a conservation check: every beat accepted on the input appears exactly once on the output, in order (a scoreboard or a formal data-tracking property). Directed/random tests: the decisive one is full-throughput streaming with stalls injected at every phase — assert s_valid continuously, toggle m_ready in every pattern (single-cycle stalls, multi-cycle, alternating, back-to-back), and confirm (a) no beat is lost, (b) no bubble appears on the input when space exists, and (c) the output is the input stream in order; then the reverse — sparse input with continuous m_ready. Formal is ideal here: prove data conservation/ordering and the no-loss/no-bubble properties exhaustively, since the state space (two beats + valids) is tiny. Coverage: all three occupancy states (EMPTY/ONE/FULL) reached, the ONE self-loop sustained (full-rate), and the FULL→ONE promote exercised. The single highest-value test is continuous input with a one-cycle m_ready stall — it simultaneously proves no-loss (skid caught the beat) and full-throughput (only one cycle of registered backpressure). A skid buffer that passes formal data-conservation plus the throughput-through-stall test is correct, and because it's a reused primitive, that proof pays off across every instance in the design.

8. Interview Questions

9. Summary

A skid buffer fully registers an AXI VALID/READY handshake — flopping both the forward (VALID/data) and backward (READY) directions — to close timing, while sustaining one beat per cycle. The key insight is that registering the backpressure makes the upstream see READY one cycle late, so a beat can be in flight when the buffer fills; a single register can't hold it (forcing data loss or a half-throughput bubble), so a second register — the skid/overflow slot — catches exactly that one in-flight beat. The canonical design sets s_ready = !skid_valid (registered backpressure: accept while the overflow slot is free), drives the output from a main register, and promotes the skid beat into main when the output is consumed. Occupancy is a tiny EMPTY/ONE/FULL FSM whose steady state is ONE with a self-loop (one in, one out, every cycle).

The cost is one cycle of latency and two registers; throughput is untouched. Two entries are provably the exact minimum for a fully-registered, full-throughput handshake. Verification centers on the throughput-through-a-stall test (continuous input, m_ready toggled) plus formal data-conservation/ordering and payload-stability properties — small enough to prove exhaustively. The skid buffer is the most-reused AXI primitive: interconnect ports, FSM outputs, FIFO front-ends, and pipeline stages all rely on it. Next, we generalize it into pipelining a handshaked path across multiple stages.

10. What Comes Next

You've built the timing-closure workhorse; next we use it to pipeline a handshaked path:

15.6 — Ready/Valid Pipelining (coming next) — chaining registered handshakes into a multi-stage pipeline without losing data or throughput, the general form of what the skid buffer does for one stage.

Previous: 15.4 — AXI Read FSM. Related: 3.1 — The VALID/READY Handshake for the contract the skid buffer registers, 3.3 — Backpressure & Stalls for the stall behavior it absorbs, and 3.5 — Handshake Dependency & Deadlock Rules for why VALID must not depend on READY.