Access-Phase Timing Anatomy

Module 4 named the access phase and walked it cycle by cycle. This chapter goes under the clock edges — it reads the access phase as a sampling cadence and pins down the single capture edge to the rising edge it happens on. The one idea to carry: PENABLE is held high for the entire access phase while the manager samples PREADY on every rising edge; the first edge where PREADY is high is completion, and it is the only edge on which PRDATA and PSLVERR are valid and captured. Everything subtle about APB read timing and error timing reduces to which edge captures what — and this chapter makes that edge exact.

1. What problem is being solved?

The problem is pinning every commit and every sample to one precise rising edge — knowing, to the clock edge, when the manager is allowed to capture PRDATA, commit a write, and read PSLVERR, while the subordinate is free to take as many cycles as it needs.

The access phase exists because a subordinate cannot always answer in one cycle, but the manager still needs a single, unambiguous instant to act on. APB solves this with a sampling cadence rather than a fixed latency: with PSEL and PENABLE already high, the manager re-reads PREADY on every rising PCLK edge of the phase. While PREADY is low the access is held — the held signals do not move and nothing is captured. The first edge where PREADY is high is the capture edge: on it, and only on it, a read latches PRDATA, a write is committed, and PSLVERR is sampled. The phase can be one edge long or ten, but the capture edge is always exactly one, and the cadence that finds it is identical every time.

2. Why the previous model is not enough

The access-phase mechanics chapter established the cycle-by-cycle picture — PENABLE high across the phase, the manager polling PREADY, PRDATA and PSLVERR valid only at completion. That model tells you the sequence of cycles. This chapter drills the next layer down: the per-cycle PREADY sampling cadence and the exact completion-edge timing of the capture. Three things the mechanics view leaves at the level of "the cycle" but a timing engineer must resolve to "the edge":

• Sampling is an action on a rising edge, not a property of a cycle. The manager does not "know" PREADY is high during a cycle — it samples PREADY at the rising edge that begins the decision. The cadence is one sample per access edge, and getting the edge wrong (sampling on the wrong phase, or on PENABLE alone) is the root of real read-data and error bugs.
• Capture is anchored to that same edge, not to the cycle's body. PRDATA is latched, the write commits, and PSLVERR is read on the single rising edge where PREADY is first seen high. Before that edge those signals are not driven; the mechanics view says "valid at completion," but the precise statement is "captured on the completion edge."
• Wait cycles stretch the cadence without restarting it. Each wait is one more sample that returned low; the access is held, but the phase is not re-entered and setup is not re-run. The number of low samples before the first high sample is the wait count — nothing else changes.

So this chapter adds the edge-level cadence: one PREADY sample per access edge, the access held on every low, and exactly one capture edge on the first high.

3. Mental model

The model: the access phase is a metronome ticking once per rising edge, and the manager reads PREADY on every tick — every "low" tick holds the access still, the first "high" tick is the capture beat.

Picture the manager standing at the access phase with PENABLE pinned high and the address and write data frozen. The clock ticks. On each tick it does exactly one thing: sample PREADY. A low sample is a held beat — nothing is captured, the frozen signals do not move, and the metronome simply ticks again. The first high sample is the beat: on that rising edge the read data is latched, the write lands, and the error status is read. After that beat the phase is over. The cadence is the same whether the first high sample arrives on the first tick or the fifth.

Three refinements make the cadence precise:

• One sample per rising edge — PREADY is the only signal read. PENABLE is constant (it cannot distinguish a held beat from a capture beat); the held address and data are constant. Only PREADY, sampled fresh on each access edge, moves the decision.
• Every low sample holds; the first high sample captures. A held beat (PREADY low) commits nothing. The capture beat (PREADY high) is the single rising edge on which PRDATA, the write commit, and PSLVERR all resolve. There is exactly one such edge per transfer.
• The capture edge is the only valid sample point for PRDATA / PSLVERR. Sampling them on any held beat reads values the subordinate is not yet driving — undefined, not merely stale. The cadence and the capture are locked to the same edge by design.

4. Real SoC / hardware context

In silicon the cadence is literal: the manager's transfer FSM parks in its access state with PENABLE asserted, and a single comparator reads PSEL & PENABLE & PREADY on every rising edge. The subordinate sets the tempo — a fast configuration register returns PREADY high on the first access edge (zero held beats); a register synchronized from another clock domain, or one reached through a bridge, returns PREADY low for a few edges while its value settles, then high. The manager's logic does not change with the subordinate's speed; it just keeps sampling until the capture edge arrives.

// APB access-phase per-cycle sampling (teaching sketch — not a full slave).
// access_complete is true on EXACTLY one rising edge per transfer: we are in
// the access phase (psel & penable) AND the subordinate is ready (pready).
wire access_complete = psel & penable & pready;
 
// The MANAGER samples PREADY on EVERY access edge. While pready is low,
// access_complete is low: the access is HELD (a wait state) — PENABLE stays
// high, the address/control/PWDATA are held stable, and NOTHING commits.
// Only on the single edge where pready is high does the manager capture
// PRDATA (read) / commit the write, and sample PSLVERR. Before that edge
// PRDATA is not driven and PSLVERR is undefined.
always_ff @(posedge pclk) begin
  if (access_complete && !pwrite) rdata_q  <= prdata;    // read data captured here only
  if (access_complete)            slverr_q <= pslverr;   // error sampled here only
end

Two properties make this robust. First, access_complete is low on every setup edge (PENABLE low) and every held beat (PREADY low), so the capture fires exactly once — the per-edge "hold or capture" decision falls out of one wire. Second, because PRDATA and PSLVERR are captured on the same rising edge the subordinate raises PREADY, the manager and subordinate never disagree about which edge the access happened on, and the manager never latches an undriven value from a held beat.

5. Engineering tradeoff table

Reading the access phase as a per-edge PREADY sample with a single capture edge is a deliberate choice. Each property trades a convenience APB does not need for the timing certainty it does.

The throughline: APB spends knowing how many edges the access takes and gains knowing exactly which edge captures everything. The cadence is identical for a zero-wait and a ten-wait access — sample PREADY each edge, hold on low, capture on the first high — which is why the manager's sampling logic stays a single wire.

6. Common RTL / waveform mistakes

7. Interview framing

This is where an interviewer checks whether you can read a stretched APB waveform to the edge, not just narrate a textbook transfer. The weak answer is "the access finishes when PREADY is high." The strong answer states the cadence and locks the capture to a single edge.

Say it in three moves: PENABLE is held high for the entire access phase, so it marks the phase, not the finish; the manager samples PREADY on every rising edge of the phase — every low sample holds the access (a wait state, nothing captured), and the first high sample is the capture edge; and PRDATA is latched, the write commits, and PSLVERR is sampled on that one capture edge, and nowhere else. Then volunteer the depth point that separates levels: the capture is locked to the rising edge PREADY is sampled high — before it PRDATA is undriven and PSLVERR is meaningless, so a block that gates on PENABLE instead of the capture edge latches garbage from a wait. What the interviewer is really probing is whether you locate the capture edge to the clock edge and understand the access phase as a per-edge PREADY cadence — exactly the skill that lets you debug a wait-state read or an error waveform. For the rule that unifies this across all completions, point to the completion contract.

8. Q&A

9. Practice

1. Read the cadence. Given an access phase with two wait states then completion, list, edge by edge, the value sampled for PREADY and whether that edge holds or captures.
2. Find the edge. On a transfer with three wait states, mark the single capture edge and explain how you found it without relying on PENABLE changing.
3. Write the wire. From memory, write access_complete = psel & penable & pready and name the three things captured only when it is high on a rising edge.
4. Place the validity. On a read that completes after one wait, mark where PRDATA becomes valid and where PSLVERR becomes meaningful, and state what a manager reads if it samples on the wait edge instead.
5. Defend the cadence. In two sentences, justify why a stale PRDATA on a wait cycle is harmless to a correct manager, and why a held beat stretches the cadence rather than restarting setup.

10. Key takeaways

• PENABLE is held high for the entire access phase — it marks the phase, never the capture edge. It rises once at the setup-to-access boundary and does not change again until the phase ends.
• The manager samples PREADY on every rising edge of the phase. Every low sample holds the access (a wait state, nothing captured); the first high sample is the capture edge. It is a per-edge cadence, not a one-shot.
• Completion is one rising edge — access_complete = psel & penable & pready, true on exactly one edge per transfer.
• PRDATA is latched, the write commits, and PSLVERR is sampled only on that capture edge. Before it, PRDATA is undriven and PSLVERR is undefined — capturing either reads garbage.
• Wait states stretch the cadence, never restart it. Each held beat is one more PREADY-low sample; PENABLE stays high and setup is never re-run.
• Gate captures on the edge, not the phase. Sampling on psel & penable & pready immunizes the manager against pre-completion garbage; sampling on PENABLE latches it.