AMBA APB · Module 5

Setup / Access Interview Traps

The classic setup/access interview gotchas as traps with the wrong answer, the right answer, and the timing reason — PENABLE assertion timing, PREADY sampling, signal stability, PENABLE-high-is-not-done, the two-cycle minimum, and back-to-back is not pipelining.

Module 5 built the two-phase model signal by signal. This capstone chapter does the thing the interview actually tests: it takes the handful of setup/access gotchas that separate candidates who memorised the spec from candidates who have debugged the bus, and drills each one as a triple — the common wrong answer, the correct answer, and the precise timing reason that decides it. The single idea to carry: every one of these traps resolves to the same two facts — PENABLE rises only at the setup-to-access boundary, and completion is PSEL & PENABLE & PREADY, never a subset. Get those two anchors right and every trap below collapses. This chapter also hands you a buggy waveform to spot, because that is exactly how a senior interviewer probes whether you can see the contract, not just recite it.

1. What problem is being solved?

The problem is defending the two-phase timing contract under pressure — being able to take any one-line claim about setup and access and immediately say whether it is true, why, and what the waveform looks like when it is violated.

In an interview you are not asked to recite signals; you are handed a plausible-sounding statement ("PENABLE goes high in setup", "single-cycle means one cycle", "PREADY is sampled once") and watched to see if you accept it. Each statement is a trap built on a real, common misreading of the timing. The skill being tested is the ability to convert the protocol's two anchors into an instant verdict:

PENABLE asserts at the setup-to-access boundary — low for the whole setup cycle, high for the access phase, and dropping on completion. It is the phase marker.
Completion is the conjunction PSEL & PENABLE & PREADY, sampled on every access cycle, with completion being the first cycle all three are high.

Every trap in this chapter is a sentence that quietly contradicts one of those two facts. Solving the chapter means being able to name which fact each trap breaks, and to point to the cycle on a waveform where the break shows.

2. Why the previous model is not enough

You already have the correct mechanics from this module: PENABLE behaviour, signal stability, and transfer completion. Each chapter is right. But knowing the rule and defending it against a confidently-worded wrong statement are different skills, and the interview tests the second one.

The mechanics view leaves three gaps that traps live in:

A correct rule stated loosely becomes a wrong answer. "The signals are stable" is true; "the signals can change after the access starts" sounds like a restatement and is the classic corruption. The trap exploits the gap between the rule and its precise boundary.
Single-signal reasoning feels authoritative and is wrong. "PENABLE is high, so the transfer is done" reasons from one signal and sounds decisive — which is exactly why it traps people. The fix is always to reach for the conjunction, not a subset.
Counting cycles the obvious way is wrong. "Single-cycle transfer" invites "one bus cycle"; the truth is two (one setup, one access) with zero wait states. The everyday meaning of the word fights the protocol meaning, and the trap is built on that collision.

So the model to add is not another signal — it is a verdict discipline: for any claim about setup/access, name the anchor it tests, give the correct answer, and cite the timing reason. The rest of this chapter is that discipline applied trap by trap.

3. Mental model

The model: every setup/access trap is a lie about one of two clocks — when PENABLE flips, or when the three-signal whistle blows. Hold those two clocks in your head and each trap announces itself.

Think of it as a checkpoint with two gates. The first gate is the setup-to-access boundary: nothing about "access" is true before it, and PENABLE is the flag that goes up exactly as you cross it — never before. The second gate is completion: the transfer is not "done" until all three guards (PSEL, PENABLE, PREADY) wave you through on the same edge, and that can be the first access cycle (zero wait) or several cycles later. A trap is always someone claiming you passed a gate you have not reached, or that a gate is a single guard when it takes three.

Three refinements sharpen the verdict:

PENABLE is a one-cycle-minimum pulse anchored to a boundary, not a level you set early. It is low in setup, rises at the boundary, holds across all access cycles, drops on completion. "High in setup" and "high two cycles in a zero-wait access" are both boundary violations.
Completion is sampled every access cycle, and it is an event, not a property of PENABLE. You read PREADY on each access edge; the first high one is completion. "PENABLE high = done" confuses the access phase with its endpoint.
Stability is anchored to completion, so "after PENABLE rises" is the start of the freeze, not permission to change. Once PENABLE is high you are inside the held window; PADDR/PWDATA are now most locked, not least.

Figure 1 — the classic 'spot the bug' interview waveform. A zero-wait transfer is drawn with PSEL high across SETUP and ACCESS, PREADY high in the single access cycle, and PADDR held stable — but PENABLE (in red) is wrong in two ways: it is already high during the SETUP cycle, and it stays high for a second cycle after the zero-wait completion. Two dashed markers flag the offending edges. The correct shape is PENABLE low for the whole setup cycle, rising at the setup-to-access boundary, high for exactly one cycle in a zero-wait access, and dropping on the completion edge. The reader's job is to name both faults and state the rule each breaks.

4. Real SoC / hardware context

These traps are not academic — each maps to a real RTL bug that ships when an engineer believes the wrong answer. In silicon the manager's transfer FSM drives PENABLE from a state register: it is deasserted in the SETUP state and asserted in the ACCESS state, so the boundary behaviour is structural, not something you time by hand. An engineer who believes "PENABLE goes high in setup" writes an FSM that asserts it one state too early, and an APB protocol checker (or a careful subordinate) rejects the access — the bug surfaces in the first integration sim.

The "PENABLE high means done" trap is the most expensive in practice: a subordinate that captures PWDATA on PENABLE alone writes during every wait cycle, committing stale or intermediate data, while the correct design gates the write on the full PSEL & PENABLE & PREADY term and writes exactly once. The "single-cycle = one cycle" trap drives throughput math wrong — an engineer sizes a DMA assuming one bus cycle per APB access and is surprised when the measured rate is half, because every access is two cycles even with zero wait states. And the "back-to-back is pipelined" trap leads someone to expect a new access to launch while the previous one is still in access, then to be confused when the waveform shows the next SETUP only after the current completion. Every trap below has this shape: a plausible belief, a concrete RTL or throughput consequence, and a timing reason that makes the correct behaviour the only legal one.

5. Engineering tradeoff table

This is the interview-trap table: each row is a gotcha as the trap statement, the wrong answer it baits, the correct answer, and the timing reason that decides it. Read it as the spine of the chapter.

Trap statement	Wrong answer (the bait)	Correct answer	Timing reason
"`PENABLE` goes high in the setup phase."	"Yes, it asserts with `PSEL`."	No — it is low through all of setup and rises only at the setup-to-access boundary.	`PENABLE` is the phase marker that defines the access phase; high in setup erases the boundary between the two phases.
"`PREADY` is sampled once, at the end."	"Sample it on the last access cycle."	No — it is sampled on every access cycle; completion is the first cycle it is high.	The manager cannot know in advance which access cycle completes, so it must check `PREADY` each cycle; the wait states are exactly the access cycles where it read low.
"You can change `PADDR`/`PWDATA` after `PENABLE` rises."	"The access started, so the bus is free."	No — once `PENABLE` is high you are inside the freeze; they hold until completion.	Stability is anchored to completion; the subordinate consumes the access at the completion edge, so a mid-access change silently commits the wrong access.
"`PENABLE` high means the transfer is complete."	"Enable high = access done."	No — `PENABLE` marks the access phase, which includes every wait cycle; completion also needs `PREADY`.	Completion is the conjunction `PSEL & PENABLE & PREADY`; `PENABLE` alone is true across waits, before anything commits.
"A single-cycle transfer is one bus cycle."	"Single-cycle = one clock."	No — it is two bus cycles (one setup, one access) with zero wait states.	The two-phase structure is mandatory; "single-cycle" names the zero-wait case, not a one-cycle access. The minimum is always 2.
"Back-to-back APB transfers are pipelined."	"The next access overlaps the current one."	No — completion may flow straight to the next setup with no idle, but accesses never overlap.	The next `SETUP` begins only after the current completion edge; adjacency removes the idle gap, it does not pipeline the phases.

The throughline: every wrong answer in the second column is a subset claim — it reasons from one signal, one cycle, or one phase, and drops a condition the protocol requires. The correct answer always restores the full term: the boundary for PENABLE, the conjunction for completion, completion-as-anchor for stability, and the mandatory two phases for cycle counting.

6. Common RTL / waveform mistakes

Misconceptions to unlearn

Trap — "PENABLE asserts in setup, alongside PSEL." Wrong. Correct: PENABLE is low for the entire setup cycle and rises at the setup-to-access boundary. Reason: PENABLE is the marker that distinguishes the two phases; asserting it in setup means there is no setup phase. This is the single most common bad-waveform fault — and the one in Figure 1.
Trap — "PREADY is sampled once." Wrong. Correct: PREADY is sampled on every access cycle, and completion is the first cycle it reads high. Reason: the subordinate decides the length by holding PREADY low (wait states); the manager has no other way to know when to commit than to check each access edge.
Trap — "After the access phase starts I can update PADDR for the next transfer." Wrong. Correct: PADDR, PWDATA, and the access-defining set are frozen from setup through completion. Reason: stability is anchored to the completion event, not to the start of access; the subordinate samples at completion, so a change after PENABLE rises corrupts the access silently — no error is raised.
Trap — "PENABLE high tells me the transfer finished." Wrong. Correct: PENABLE high only means you are in the access phase; the transfer finishes when PSEL & PENABLE & PREADY are all high. Reason: with wait states, PENABLE is high for cycles where nothing has committed; gating a write on PENABLE alone writes during waits.
Trap — "A zero-wait access takes one cycle, so PENABLE is high for one boundary edge only." Wrong. Correct: a zero-wait transfer is still two bus cycles, and PENABLE is high for exactly one of them (the access cycle). Reason: the two-phase structure is non-negotiable; "single-cycle" is shorthand for zero wait states, and PENABLE holding two access cycles in a zero-wait transfer (Figure 1's second fault) is illegal.
Trap — "Back-to-back transfers overlap, so APB pipelines like AXI." Wrong. Correct: adjacency removes the idle gap but the next access's setup begins only after the current completion; phases never overlap. Reason: APB is a non-pipelined, single-outstanding bus by construction — there is no mechanism for two accesses in flight.

Figure 2 — the corrected waveform beside the trap. Both diagrams show the same zero-wait transfer with PSEL high across setup and access, PREADY high in the access cycle, and PADDR held. Top (correct): PENABLE is low through the whole SETUP cycle, rises at the setup-to-access boundary, is high for exactly one ACCESS cycle, and drops on the completion edge — annotated 'low in SETUP' and 'one ACCESS cycle, drops at completion'. Bottom (trap): PENABLE (red) is high already in SETUP and stays high a second cycle, with markers flagging the early assertion ('early') and the missing drop after completion ('no drop'). Placing the fix beside the fault shows the exact two-phase shape PENABLE must take.

7. Interview framing

This is the chapter the rest of Module 5 exists to support, because setup/access timing is the most-asked APB topic and the questions are almost always traps. An interviewer rarely asks "explain the access phase"; they assert something slightly wrong and watch whether you catch it. Your job is to catch it and explain the catch crisply.

The framing that lands every time is the wrong/correct/reason triple, spoken out loud. When handed a trap, do not just say "that is wrong" — say "the common belief is X; the correct timing is Y; the reason is Z," tying Z to one of the two anchors. For example: "The belief is PENABLE goes high in setup; the correct timing is it rises at the setup-to-access boundary and is low through all of setup; the reason is PENABLE is the phase marker, so asserting it in setup means there is no setup phase." That structure proves you are not reciting — you are reasoning from the contract. The strongest single move is to volunteer the unifying point: every setup/access trap is either a PENABLE-boundary error or a completion-conjunction error, and you resolve it by restoring the full term. If you can also sketch the bad waveform and point to the offending edge (as in Figure 1), the interviewer knows you have debugged the bus, not just read about it.

8. Q&A

9. Practice

Verdict drill. For each trap in the §5 table, cover the last three columns and, from the statement alone, say "wrong answer / correct answer / timing reason" out loud. Repeat until each is instant.
Spot the bug. From Figure 1, name both faults on PENABLE and state the precise rule each one breaks. Then redraw the correct PENABLE for the same zero-wait transfer.
Name the anchor. Given a new trap ("PRDATA is valid as soon as PENABLE rises"), state which of the two anchors it tests and give the wrong/correct/reason triple.
Count the cycles. For a transfer with two wait states, count the total bus cycles, the number of access cycles, the number of cycles PENABLE is high, and the single completion cycle — and explain why "single-cycle" would have given a different count.
Defend under pressure. A reviewer insists "back-to-back proves APB is pipelined." In two sentences, refute it and state when the next access's setup actually begins relative to the current completion.

10. Key takeaways

Every setup/access trap is one of two errors: a PENABLE-boundary mistake (asserting early, holding late) or a completion-conjunction mistake (treating a subset as "done"). Name the error and the answer follows.
PENABLE is a phase marker, not a level you set early. Low through all of setup, rises at the setup-to-access boundary, high across access, drops on completion — including exactly one high cycle in a zero-wait access.
PREADY is sampled every access cycle; completion is the first high. The wait states are the access cycles where it read low. Completion is never PENABLE alone — it is PSEL & PENABLE & PREADY on one edge.
Stability is anchored to completion, so "after PENABLE rises" is the freeze, not freedom. Changing PADDR/PWDATA mid-access silently commits the wrong access with no error.
"Single-cycle" means zero wait states, not one cycle. Every APB transfer is at least two bus cycles (setup + access); the minimum is structural and non-negotiable.
Back-to-back is adjacency, not pipelining. The next setup begins only after the current completion; APB is non-pipelined and single-outstanding, so accesses never overlap.