Two-Phase Timing Diagrams

Modules 2, 4, and 5 gave you the rules: setup presents the access, the access phase performs it, completion is PSEL & PENABLE & PREADY, and the access-defining signals hold stable until that edge. This capstone chapter converts those rules into a skill — a repeatable method for reading any two-phase APB waveform from left to right and saying exactly what it does. The single idea to carry: you do not read an APB waveform signal by signal; you read it phase by phase, locating the two phase boundaries first, then the completion edge, then the held-stable bands — always in the same order, whether the transfer has zero wait states, ten, or a bug.

1. What problem is being solved?

The problem is turning a wall of waveform rows into a precise, repeatable reading — the same five answers every time, no matter how the transfer is stretched or broken.

A two-phase APB transfer is a small number of rows (PSEL, PENABLE, PWRITE, PADDR, PWDATA/PRDATA, PREADY) over a handful of cycles, but a beginner reads them in the wrong order and draws the wrong conclusion. They look at PENABLE high and say "the transfer happened" — but PENABLE is high across every wait cycle. They look at the address appearing and say "it started here" — but nothing commits at address-time. The fix is a fixed reading order that maps each waveform feature to a protocol fact:

• PSEL rising → the SETUP boundary. This is where the transfer begins and the access is presented but not yet enabled.
• PENABLE rising → the ACCESS boundary. This is where the access is performed; it stays high for the whole access phase, waits included.
• PREADY → the cadence and the completion edge. Low cycles in access are wait states; the first high access cycle is the one completion edge.
• PADDR/PWRITE/PWDATA → the held-stable band. These must be frozen from the setup edge through completion.

Read in that order, every legal waveform interprets itself, and every illegal one fails a specific step.

2. Why the previous model is not enough

You arrive here with the rules already correct in isolation: setup-phase timing tells you what PSEL-high-PENABLE-low means, access-phase timing tells you what PENABLE high means, transfer-completion tells you the completion edge is PSEL & PENABLE & PREADY, and signal-stability tells you which signals freeze. Each is a rule. None of them, by itself, is a procedure — and an engineer in front of an unfamiliar waveform needs a procedure, not a list of facts.

The gap is three-fold:

• The rules are unordered; reading must be ordered. Knowing all four facts does not tell you which to apply first. Apply them in the wrong order — checking stability before you have located the phases — and you cannot even say which cycles the stability rule covers. The phases must be located before anything else can be judged.
• The rules describe one transfer; waveforms vary. A rule says "completion is PREADY high in access." A real waveform might insert zero, one, or many wait cycles, so "find completion" is a search you must perform, not a fixed cycle you can memorise. The method has to be wait-count-agnostic.
• The rules assume a legal transfer; debugging starts from a broken one. Every rule above is stated for a correct waveform. Debugging means reading a waveform that violates one of them, and you need the same procedure to localise which rule broke — not a separate skill.

So the model to add is not another rule. It is the discipline of reading: a fixed five-step pass that takes the rules you already know and makes them a method you can run on any waveform, legal or not.

3. Mental model

The model: read an APB waveform like a sentence with known grammar — find the subject, the verb, then check the agreement. PSEL is "who" (the subordinate is selected), PENABLE is "the action is happening," PREADY is "the action finished," and the held signals are the object that must not change while the verb is in progress.

Picture scanning the waveform left to right with five questions on a card, asked in order. You do not stare at all the rows at once; you ask question one, mark the answer on the waveform, then move to question two. By the time you reach question five you have already drawn the phase boundaries and the completion edge, so verifying the held-stable band is trivial — you know exactly the span it must cover.

Three refinements make the method precise:

• Phases first, edge second, bands last. Always locate PSEL-rise (SETUP) and PENABLE-rise (ACCESS) before searching for completion, because the completion search is only meaningful inside the access phase. Then the stability span is fully determined: setup edge to completion edge.
• The completion edge is found by search, not by position. Walk the access cycles left to right; the first one with PREADY high is completion. Count the PREADY-low ones before it — that is the wait-state count. The procedure is identical for zero waits and ten.
• A broken waveform fails exactly one question. No PSEL-rise means no real transfer; PENABLE high without PSEL is an illegal access; no PREADY-high access cycle is a hung transfer; a moving PADDR/PWDATA mid-access is silent corruption. The same five questions localise the fault to one step.

4. Real SoC / hardware context

In practice you run this method on a simulation waveform or a logic-analyser capture during bring-up, and the two transfers below are the two cases you will read constantly: the zero-wait transfer (the common case, fast subordinate) and the multi-wait transfer (a slow subordinate inserting backpressure). Reading them with the same five questions is the whole point — the method does not change, only the wait count does.

The zero-wait transfer. PSEL rises out of IDLE into SETUP with PENABLE low — that is question 1. One cycle later PENABLE rises into ACCESS — question 2. Because the subordinate is fast, it drives PREADY high on that same access cycle, so there are no PREADY-low cycles (question 3 answers "none") and the very first access cycle is completion (question 4). The address and write data are held across the two cycles (question 5). This is the shortest legal two-phase transfer: one setup cycle, one access cycle, completion on the second.

The multi-wait transfer. The reading is the same up to question 3, where it diverges: PENABLE is held high across three access cycles, and PREADY is sampled low on the first two — those are the wait states — and high only on the third. Question 4 therefore lands on the third access cycle as the single completion edge, and question 5 verifies that PADDR/PWDATA held byte-for-byte across all of access, waits included. The same five questions, applied identically, read a transfer of any length.

5. Engineering tradeoff table

The five-question method is a deliberate reading discipline. Each step trades a tempting shortcut for a reading that stays correct on every waveform.

The throughline: by always reading phases first and the completion edge by search, the method is immune to the two things that vary — wait-state count and whether the waveform is legal — so the same five questions cover the common case, the slow-subordinate case, and the bug.

6. Common RTL / waveform mistakes

7. Interview framing

Interviewers test this by sliding a waveform across the table and asking "read this APB transfer" or "is this legal — and how do you know?" The weak candidate points at random signals; the strong one runs a visible, ordered method and narrates each step. Demonstrating the procedure is the answer.

Say it as the five-step pass: find where PSEL rises — that is SETUP; find where PENABLE rises — that is ACCESS; walk the access cycles and the PREADY-low ones are wait states; the first PREADY-high access cycle is the single completion edge where the write commits or PRDATA/PSLVERR are sampled; then verify PADDR/PWRITE/PWDATA held byte-for-byte from the setup edge through completion. The depth signal that lands: state that the method is identical for zero waits and ten — completion is found by searching for the first PREADY-high cycle, not by a fixed position — and that the same five questions localise a broken waveform to the one step it fails. An interviewer hears a repeatable engineering method, not memorised trivia.

8. Q&A

9. Practice

1. Run the five questions. Take the zero-wait waveform (Figure 2) and write the five answers in order: where PSEL rises, where PENABLE rises, how many PREADY-low waits, which cycle is completion, and whether the band held.
2. Re-run on the multi-wait case. Do the same for Figure 3 and confirm only the wait-count answer differs from the zero-wait case.
3. Count the waits. Given an access phase where PENABLE is high for four cycles and PREADY is high only on the fourth, state the wait-state count and the completion cycle.
4. Localise the break. For a waveform where PENABLE goes high but PSEL is low, name which of the five questions fails and what the fault is.
5. Spot the silent one. Given a one-wait transfer where PADDR changes on the wait cycle, state which question fails, what the subordinate commits, and whether APB raises an error.

10. Key takeaways

• Read an APB waveform phase by phase, not signal by signal — locate the two phase boundaries first, then the completion edge, then the held-stable bands, always in that order.
• PSEL rising is SETUP; PENABLE rising is ACCESS. The PENABLE edge is the SETUP-to-ACCESS boundary, and PENABLE stays high across the whole access phase, waits included.
• Find completion by searching, not by position — the first access cycle where PREADY is high is the single completion edge; the PREADY-low access cycles before it are wait states.
• The method is wait-count-agnostic. Zero waits or ten, the same five questions apply identically; only the count of PREADY-low cycles differs.
• Verify the band last, with a known span. PADDR/PWRITE/PWDATA must hold byte-for-byte from the setup edge through completion — checked on every access cycle, not just at the edge.
• One method reads legal and broken waveforms. A broken transfer fails exactly one of the five questions, so the same reading pass localises the fault to a single step.