AMBA AXI · Module 13

Burst Efficiency

How burst length and transfer width shape AXI efficiency — address-phase overhead amortized by long bursts, the efficiency-vs-length curve, the lane waste of narrow transfers, and why long full-width bursts maximize throughput.

Chapter 13.1 named short bursts and narrow transfers as throughput limiters; this chapter quantifies them. Burst efficiency is how much of the bus's potential a transaction actually uses — and it's shaped by two factors: burst length (long bursts amortize the per-transaction address overhead) and transfer width (full-width beats use all byte lanes; narrow ones waste them). The takeaway is simple and practical — long, full-width bursts maximize efficiency — but the why (the amortization math and the lane-waste arithmetic) is what lets you size bursts and diagnose efficiency losses.

1. Address Overhead and Amortization

Every transaction has an address phase (and handshake overhead) that costs cycles but moves no data. A burst amortizes that fixed cost over its data beats: the more beats per address, the smaller the overhead's share. Roughly:

Efficiency ≈ N / (N + overhead), where N = beats and overhead = the non-data cycles per transaction.

So a length-1 burst pays the full address overhead for a single beat (if the address costs ~1 cycle, that's 1/(1+1) ≈ 50% — half the cycles are overhead). A 16-beat burst is 16/17 ≈ 94%; a 256-beat burst (AXI4 max INCR) is 256/257 ≈ 99.6%. The overhead is fixed per transaction, so longer bursts drive efficiency toward 100% by spreading it thinner. This is the reason AXI is burst-based and why short bursts are a performance anti-pattern.

burst-efficiency — address overhead amortized over 4 data beats

6 cycles

Figure 1 — burst-efficiency: address overhead amortized over data beats. The address phase (a non-data cycle) is fixed per transaction; a 4-beat burst spends 1 overhead cycle for 4 data beats (≈80% efficient). Longer bursts spread the fixed overhead thinner — 16 beats ≈94%, 256 beats ≈99.6%. Short bursts pay the overhead per few beats and waste cycles.

2. The Efficiency-vs-Length Curve

Plotting efficiency against burst length gives a rising, saturating curve:

Short bursts (1–4 beats): efficiency is low (50–80%) — the overhead is a large fraction. Each added beat helps a lot.
Medium bursts (8–16 beats): efficiency is good (89–94%) — diminishing but still meaningful gains.
Long bursts (64–256 beats): efficiency approaches the asymptote (~98–99.6%) — further length adds almost nothing.

So there's a sweet spot: most of the efficiency gain comes in the first 16 beats; beyond that the curve flattens. The practical limits cap the maximum — 256 beats (AXI4 INCR) and the 4 KB boundary (Chapter 7.6) — so bursts can't be arbitrarily long, but they don't need to be: 16–64 beats usually captures ~95%+ efficiency. The takeaway: avoid short bursts (the steep part of the curve), and use moderately long bursts to reach the flat part — you don't need the absolute maximum.

Figure 2 — the efficiency-vs-length curve. Efficiency rises with burst length and saturates: short bursts (1–4) are 50–80% (steep gains per beat), medium (8–16) are ~89–94%, long (64–256) approach ~99%. Most gain is in the first ~16 beats; beyond that it flattens. Capped by 256 beats / the 4 KB rule. Avoid the steep (short) region; moderate length captures most efficiency.

3. Narrow Transfers Waste Lanes

The second efficiency factor is transfer width. A narrow transfer (AxSIZE below the bus width, Chapter 7.7) uses only some byte lanes per beat, so even at full beat-rate it moves less than the bus could:

Lane efficiency = bytes per beat (2^AxSIZE) ÷ bus width bytes

A 1-byte/beat transfer on a 64-bit (8-byte) bus is 1/8 = 12.5% lane efficiency — 7 of 8 lanes idle every beat. A 4-byte/beat transfer on the same bus is 4/8 = 50%. Full-width (2^AxSIZE = bus width) is 100% — all lanes used. So narrow transfers waste bandwidth per beat, independent of burst length: a long narrow burst amortizes the address overhead but still only fills part of the bus each beat.

The two factors multiply: total efficiency ≈ (length factor) × (width factor). A short narrow burst is doubly bad (low on both); a long full-width burst is doubly good. So the recipe is both long and full-width — and narrow transfers are only worth it when the data genuinely is sub-width (a byte-wide peripheral) or when alignment forces partial edge beats.

Figure 3 — narrow transfers waste byte lanes. Lane efficiency = bytes-per-beat ÷ bus-width: a 1-byte/beat transfer on an 8-byte bus uses 1/8 of the lanes (12.5%); 4-byte/beat is 50%; full-width is 100%. Narrow wastes bandwidth every beat regardless of burst length. Total efficiency ≈ length-factor × width-factor — so maximize both: long AND full-width.

4. Maximizing Efficiency in Practice

The combined recipe and the trade-offs:

Figure 4 — maximizing efficiency. Use long bursts (amortize address overhead — toward the flat part of the curve) AND full-width transfers (use all byte lanes). Total efficiency ≈ length-factor × width-factor. Bounded by 256 beats / 4 KB and by the data's natural width/alignment. Short and/or narrow bursts are the efficiency anti-patterns.

The practical guidance: a high-throughput master (DMA, accelerator) should issue long, full-width, aligned bursts — typically the largest the 4 KB rule allows for the access, full bus width, aligned to avoid partial edge beats. The limits: the 4 KB boundary caps length per region (split there, Chapter 7.6), the 256-beat maximum (INCR), the data's natural width (a byte-stream peripheral is inherently narrow), and alignment (unaligned starts add partial first/last beats — minor, but real). Combine high burst efficiency with sufficient outstanding depth (Chapter 13.3) to hide latency, and you reach near-peak sustained throughput (Chapter 13.1). Burst efficiency is the per-transaction efficiency; outstanding depth keeps those efficient transactions flowing.

5. Common Misconceptions

Myths to unlearn

"Burst length doesn't matter if I do many bursts." It does — each burst pays the address overhead, so short bursts waste a large fraction of cycles. Efficiency ≈ N/(N+overhead); short N is low.
"Efficiency keeps rising with length." It saturates — most gain is in the first ~16 beats, then the curve flattens. You don't need the 256-beat maximum to get ~95%+.
"Narrow transfers only matter for small data." A narrow transfer wastes byte lanes every beat (2^AxSIZE ÷ bus-width), regardless of how long the burst is. Use full-width unless the data is genuinely sub-width.
"Length and width are independent knobs." Their efficiency factors multiply — total ≈ length-factor × width-factor. A short narrow burst is doubly bad.
"Burst efficiency alone gives peak throughput." It's the per-transaction efficiency; you still need outstanding depth to hide latency (13.3). Efficient bursts that aren't kept flowing are still latency-bound.
"Longer is always better, no downside." Bounded by the 4 KB rule, the 256-beat limit, and the data's nature; and very long bursts can hurt latency/fairness (one master holds a port longer). The sweet spot is moderate length.

6. Debugging Insight

🔍 Debugging insight — quantify the length and width efficiency losses

When efficiency is low, separate the length and width contributions:

Compute the length factor — N/(N+overhead) from the actual burst length. If bursts are short (1–4 beats), this alone could be 50–80% — increase burst length toward the flat part of the curve (8–64 beats).
Compute the width factor — 2^AxSIZE ÷ bus-width. If AxSIZE is below the bus width, you're wasting lanes (e.g., 4-byte beats on a 16-byte bus = 25%). Use full-width transfers unless the data is sub-width.
Multiply them — total ≈ length × width. A "20% efficient" path might be 50% length × 40% width — both need fixing, and the product tells you the headroom.
Throughput low but bursts already long and full-width? Burst efficiency isn't the problem — look at outstanding depth (latency-bound, 13.3) or contention (12.4). Burst efficiency is per-transaction; it doesn't cover latency hiding.
Partial beats on every burst? Unaligned starts (Chapter 7.7) add partial first/last beats — minor, but align the bursts if it matters.

The triage: low efficiency → compute length factor and width factor separately; short → lengthen; narrow → widen; both-good-but-still-slow → it's depth or contention, not burst efficiency. The two factors are independently measurable and fixable.

7. Verification Insight

✅ Verification insight — measure efficiency vs burst length and width

Burst efficiency is a performance property measured by sweeping the burst parameters. Build monitors that compute per-transaction efficiency (useful data bytes ÷ bus-cycles consumed) and characterize it against burst length (sweep 1 → max; confirm the rising, saturating curve and that the design's typical length is on the flat part) and transfer width (sweep AxSIZE; confirm lane efficiency = 2^AxSIZE ÷ bus-width). Assert the master's actual traffic uses efficient bursts — a DMA that's supposed to do 16-beat full-width bursts but is configured for length-1 is a (silent) performance bug.

Coverage should include: each burst length (the efficiency curve), each AxSIZE (the width factor), the combined short-narrow worst case, long-full-width best case, unaligned bursts (partial-beat overhead), and the design's realistic burst-shape mix (the actual expected efficiency). The highest-value test is measuring the design's typical burst shape's efficiency and confirming it's near the achievable maximum — because a master shaping short or narrow bursts works correctly (functional tests pass) but wastes most of the bus, a classic correct-but-slow bug. Pair this with the outstanding-depth sweep (13.3): together they confirm both per-transaction efficiency (good burst shape) and sustained throughput (enough depth to keep efficient bursts flowing) — the two halves of reaching peak.

8. Interview Questions

9. Summary

Burst efficiency — how much of the bus a transaction actually uses — is governed by two multiplicative factors. Burst length sets the length factor N/(N+overhead): the fixed address overhead is amortized over the beats, so length-1 is ~50%, 16 beats ~94%, 256 beats ~99.6% — a rising, saturating curve where most gain is in the first ~16 beats. Transfer width sets the width factor 2^AxSIZE ÷ bus-width: a narrow transfer wastes the unused byte lanes every beat (1-byte/beat on an 8-byte bus = 12.5%), while full-width is 100%. Total efficiency ≈ length × width, so the recipe is long, full-width, aligned bursts, bounded by the 4 KB rule, the 256-beat limit, and the data's natural width.

Critically, burst efficiency is a per-transaction metric — it ensures no waste within a transaction — but sustained throughput also needs outstanding depth (Chapter 13.3) to hide latency and keep efficient bursts flowing (no idle gaps between them). So sustained ≈ peak × burst-efficiency × utilization, the two factors complementary. Diagnose efficiency by computing the length and width factors separately (short → lengthen, narrow → widen); if both are good but throughput is still low, the problem is depth or contention, not burst shape. Next: backpressure and pipeline effects — how stalls further shape achievable throughput.

10. What Comes Next

You've got per-transaction efficiency; next, how stalls shape throughput:

13.5 — Backpressure & Pipeline Effects (coming next) — quantifying how READY stalls and pipelining shape the achievable throughput.
13.6 — Identifying Performance Bottlenecks (coming soon) — a method to locate the limiting stage in an AXI path.

Previous: 13.3 — Outstanding Depth & Buffering. Related: 7.1 — Burst Length, Size & Beats and 7.7 — Narrow & Unaligned Transfers for the underlying mechanics. For the broader protocol catalog, see the AMBA family overview doc.