AMBA AXI · Module 7

Burst Length, Size & Beats

The foundation of AXI data transfer — what a beat is, how burst length is AxLEN+1, how transfer size is 2^AxSIZE bytes per beat, the total-bytes formula, and the AXI3 vs AXI4 length limits.

AXI is a burst-based protocol: a single address transaction can move many data items. Module 6 introduced AxLEN and AxSIZE as signals; this module treats bursts as first-class, and it starts here with the three quantities every burst is built from — the beat, the burst length, and the transfer size. Getting these exactly right is foundational: every burst type, every per-beat address, the 4 KB rule, and narrow/unaligned handling in the rest of Module 7 are arithmetic on top of these definitions. This chapter pins down each term, the formulas that connect them, and the AXI3↔AXI4 limits.

1. The Beat — One Data Transfer

A beat is a single data transfer on a data channel — one successful VALID/READY handshake that moves up to one bus-width of data. On the write-data channel a beat is one WVALID&WREADY cycle carrying one WDATA word (with its WSTRB); on the read-data channel a beat is one RVALID&RREADY cycle carrying one RDATA word (with its RRESP). "Beat" is AXI's unit of data; a burst is just an ordered sequence of beats sharing one address transaction.

The width of a beat — how many bytes it can carry — is set by AxSIZE (Section 3), and is at most the data bus width. The number of beats is set by AxLEN (Section 2).

Figure 1 — one address transaction expands into a burst of beats. A single AW/AR address handshake is followed by AxLEN+1 data beats on the W or R channel, each beat one VALID/READY transfer of up to 2^AxSIZE bytes. The beat is AXI's unit of data; the burst is the sequence sharing one address.

2. Burst Length — AxLEN + 1

The burst length is the number of beats in the burst, and it is AxLEN + 1. AxLEN is the encoded value, offset by one so that the minimum legal burst (one beat) is encoded as AxLEN = 0:

`AxLEN`	Beats in burst
`0`	1
`1`	2
`3`	4
`15`	16
`255`	256 (AXI4 INCR only)

The "+1" is the single most common off-by-one in AXI: a burst of 4 beats is AxLEN = 3, not 4. The field width — and therefore the maximum length — differs by version and burst type (Section 5).

3. Transfer Size — 2^AxSIZE Bytes per Beat

AxSIZE sets the number of bytes transferred per beat, as a power of two: bytes/beat = 2^AxSIZE. It must not exceed the data bus width.

`AxSIZE`	Bytes per beat
`0`	1
`1`	2
`2`	4
`3`	8
`4`	16
`5`	32
`6`	64
`7`	128

A beat whose AxSIZE equals the full bus width is a full-width transfer (all byte lanes usable); a smaller AxSIZE is a narrow transfer that uses only some lanes each beat (Chapter 7.7). AxSIZE is fixed for the whole burst — every beat is the same size.

burst-beats — 4-beat burst (AxLEN=3), 4 bytes/beat (AxSIZE=2)

6 cycles

Figure 2 — burst-beats: a 4-beat INCR read burst with AxLEN=3 and AxSIZE=2 (4 bytes/beat). One address handshake yields four R beats (D0–D3), each a VALID/READY transfer; RLAST marks the fourth. Burst length = AxLEN+1 = 4; each beat carries 2^AxSIZE = 4 bytes.

4. Total Data and Why Bursts Exist

The total data a burst moves follows directly:

bytes transferred ≈ (AxLEN + 1) × 2^AxSIZE

i.e., beats × bytes-per-beat. (For INCR/WRAP the address advances across those bytes; for FIXED the same address is rewritten each beat — same byte count, different addressing, Chapter 7.2.) A full-width 64-bit bus (AxSIZE = 3, 8 bytes) doing a 16-beat burst (AxLEN = 15) moves 16 × 8 = 128 bytes from one address transaction.

That "one address transaction" is the whole point. Bursts amortize the address-phase and arbitration overhead across many beats: the manager arbitrates and issues an address once, then streams AxLEN+1 beats. This is what makes AXI efficient for memory and DMA traffic — without bursts, every data word would pay a full address handshake and arbitration round.

Figure 3 — why AXI is burst-based. A single address transaction (one arbitration, one address handshake) amortizes over AxLEN+1 beats of 2^AxSIZE bytes each. The per-transfer overhead is paid once, not per word — the basis of AXI's memory/DMA efficiency.

5. AXI3 vs AXI4 Length Limits

The maximum burst length depends on the version and the burst type:

	`AxLEN` width	INCR max	FIXED / WRAP max
AXI3	4 bits	16 beats	16 beats
AXI4	8 bits	256 beats	16 beats

AXI4 widened AxLEN to 8 bits and raised the INCR ceiling to 256 beats, while FIXED and WRAP remain capped at 16 beats (a WRAP length must also be 2, 4, 8, or 16 — Chapter 7.4). AXI3's uniform limit was 16 beats for all types. This matters at AXI3↔AXI4 bridges: a 256-beat AXI4 INCR burst cannot pass through to an AXI3 side unchanged — it must be split into ≤16-beat bursts. (And independently of length, no burst may cross a 4 KB address boundary — Chapter 7.6.)

Figure 4 — burst-length limits by version and type. AXI3 caps all types at 16 beats (4-bit AxLEN). AXI4 widens AxLEN to 8 bits, raising INCR to 256 beats while FIXED and WRAP stay at 16 (WRAP restricted to 2/4/8/16). A long AXI4 INCR burst therefore must be split when bridged down to AXI3.

6. Common Misconceptions

Myths to unlearn

"AxLEN is the number of beats." It's AxLEN + 1. A 4-beat burst is AxLEN = 3. The off-by-one is the classic burst bug.
"AxSIZE is the total transfer size." No — AxSIZE is bytes per beat (2^AxSIZE); total bytes is (AxLEN+1) × 2^AxSIZE.
"A burst can be any length." No — INCR is ≤256 beats (AXI4) / ≤16 (AXI3); FIXED/WRAP are ≤16; WRAP must be 2/4/8/16; and no burst may cross a 4 KB boundary.
"AxSIZE can exceed the bus width." It cannot — 2^AxSIZE must be ≤ the data bus width in bytes. Equal to the width is full-width; less is a narrow transfer.
"Beats in a burst can have different sizes." No — AxSIZE (and burst type) are fixed for the whole burst; every beat is 2^AxSIZE bytes.
"More beats always means more bytes than a bigger AxSIZE." They trade off — throughput depends on both (AxLEN+1) and 2^AxSIZE; a few wide beats can move as much as many narrow ones.

7. Debugging Insight

🔍 Debugging insight — burst-arithmetic errors are the root of length and size bugs

Most "burst" bugs reduce to a miscount of beats or bytes:

Burst ends one beat short or one too long? The AxLEN +1 off-by-one — a master encoding "4 beats" as AxLEN=4 issues 5 beats; encoding it as AxLEN=3 is correct. Cross-check the beat count (and where LAST lands) against AxLEN+1.
Wrong number of bytes moved / data misaligned per beat? Check AxSIZE: bytes/beat is 2^AxSIZE, not AxSIZE. A master that drives AxSIZE=4 expecting 4 bytes actually requests 16 bytes/beat — quadruple the data and wrong lane usage.
A long AXI4 burst breaks through a bridge to AXI3? The length limit — AXI3 caps at 16 beats, so a 256-beat INCR must be split. An un-split long burst is illegal on the AXI3 side.
AxSIZE larger than the bus? Illegal — 2^AxSIZE must fit the data width. A 32-bit bus (AxSIZE ≤ 2) driven with AxSIZE=3 (8 bytes) is malformed.
Throughput far below expectation? Possibly tiny bursts (length 1) paying full address overhead per word — the anti-pattern bursts exist to avoid. Check AxLEN.

The throughline: convert the symptom to (AxLEN+1) beats and 2^AxSIZE bytes and the discrepancy usually jumps out. These three quantities are the arithmetic the rest of Module 7 builds on.

8. Verification Insight

✅ Verification insight — beat counting, size legality, and length-limit coverage

The core checks are arithmetic and boundary conditions. Beat counting: assert the burst delivers exactly AxLEN+1 beats with LAST on the final one (ties directly to the WLAST/RLAST checks of Chapter 6.8). Size legality: 2^AxSIZE must not exceed the data bus width, and AxSIZE must be constant across the burst. Length legality: enforce the per-type/per-version limits — INCR ≤256 (AXI4) / ≤16 (AXI3), FIXED/WRAP ≤16, WRAP ∈ 16. Coverage should sweep the boundaries: length 1 (AxLEN=0, where LAST is on the first beat), the maximum length for each type, the minimum and maximum AxSIZE the bus allows, and full-width vs narrow beats.

A byte-accurate scoreboard should reconcile the total bytes (AxLEN+1) × 2^AxSIZE against the data actually transferred — a mismatch catches both the +1 and the 2^AxSIZE errors at once. The highest-value directed tests are the limit edges (max-length INCR, the AXI3 16-beat cap, an over-wide AxSIZE) since those expose bridge/splitter and decoder bugs. Address progression and the 4 KB boundary are verified in their own chapters; here the target is counts and sizes.

9. Interview Questions

10. Summary

Every AXI burst is built from three quantities. A beat is a single VALID/READY data transfer — AXI's unit of data. The burst length is AxLEN + 1 beats (the +1 offset so 1 beat = AxLEN 0; mind the off-by-one). The transfer size is 2^AxSIZE bytes per beat, constant across the burst and never exceeding the bus width. Together they move (AxLEN+1) × 2^AxSIZE bytes from a single address transaction — and that amortization of address/arbitration overhead over many beats is the entire reason AXI is burst-based and efficient for memory and DMA. The limits differ by version: AXI3 caps every type at 16 beats; AXI4 raises INCR to 256 while FIXED/WRAP stay at 16 (WRAP ∈ 16).

These definitions are the arithmetic foundation for the rest of Module 7: the burst types (FIXED/INCR/WRAP), per-beat address calculation, the 4 KB boundary rule, and narrow/unaligned transfers are all computations on beats, length, and size. Debug and verify them by converting any symptom back to (AxLEN+1) beats and 2^AxSIZE bytes. Next: the first burst type, FIXED — where every beat reuses the same address.

11. What Comes Next

You've got the burst foundation; next, the three burst types, starting with FIXED:

7.2 — FIXED Bursts (coming next) — the burst where every beat reuses the same address, and its FIFO/peripheral use case.
7.3 — INCR Bursts (coming soon) — the incrementing workhorse for memory access.

Previous: 6.8 — RESP & LAST Signals. Related: 6.1 — AxADDR, AxLEN & AxSIZE for the signals, and 6.2 — AxBURST for the burst-type selector. For the broader protocol catalog, see the AMBA family overview doc.