AMBA AXI · Module 7

FIXED Bursts

The AXI FIXED burst (AxBURST=00) — every beat targets the same address, why that's exactly what a peripheral FIFO or register needs, how it contrasts with INCR, and its constraints.

The first of AXI's three burst types is the simplest in its addressing and the most special-purpose: the FIXED burst (AxBURST = 2'b00), where every beat targets the same address. The address does not advance from beat to beat. That sounds useless for memory — and it is — but it's precisely what you want when the target is a single hardware location that absorbs or produces a stream of data: a peripheral FIFO or a repeatedly-accessed register. This chapter covers what FIXED does, the use case that justifies it, how it contrasts with INCR, and its constraints.

1. What a FIXED Burst Is

In a FIXED burst the same address is used for every beat of the burst. The manager issues one address (AxADDR) and AxBURST = 2'b00; the subordinate then accepts/produces AxLEN+1 beats, all to that one address. Nothing about the addressing changes between beats — beat 0, beat 1, … beat AxLEN all hit AxADDR.

Everything else behaves as usual: AxSIZE still sets the bytes per beat, the byte lanes used are those the address and size select (the same lanes each beat, since the address is constant), WSTRB is still per beat, and LAST still marks the final beat. Only the address progression is different — and "no progression" is the whole definition.

Figure 1 — a FIXED burst (AxBURST=00). One address transaction names a single address A; every one of the AxLEN+1 beats reads or writes that same address A — no increment. Contrast this with INCR, where each beat advances. FIXED is for a single fixed-location target, not a memory range.

2. A FIXED Write on the Wire

Here a 4-beat FIXED write pushes four words into a FIFO at address 0x4000 — one address transaction, four data beats, all to the same location:

fixed-burst — 4-beat FIXED write to a FIFO at 0x4000

6 cycles

Figure 2 — fixed-burst: a 4-beat FIXED write (AxLEN=3, AxBURST=00) to a FIFO at 0x4000. The address is issued once with AWBURST=FIXED; the four W beats (D0–D3) all write 0x4000, with WLAST on the last. The data streams beat by beat exactly like any burst — only the address stays put.

3. The Use Case — FIFOs and Peripheral Ports

FIXED exists for targets that are a single location, not a range of memory. The canonical case is a peripheral FIFO: a hardware queue exposes one data port at one address; pushing N words means writing that one address N times, and draining N words means reading it N times. A FIXED burst expresses exactly that — "do AxLEN+1 accesses to this one port" — in a single transaction, so a DMA engine can stream to/from a peripheral's FIFO without issuing a separate address for every word.

Other fits: any memory-mapped register or device port where repeated access to the same address is the intent (e.g., draining a status FIFO, feeding a serializer's data register). The defining test is: does the data belong at one fixed location, or spread across addresses? One location → FIXED; a range → INCR.

Figure 3 — the FIXED use case. A DMA engine streams a burst into a peripheral's single FIFO port: one address (the FIFO data register), many beats, each pushing one word into the queue. INCR would wrongly scatter the words across ascending addresses; FIXED keeps every beat aimed at the one port the FIFO presents.

4. FIXED vs INCR

The contrast with INCR (Chapter 7.3) is the clearest way to fix FIXED in mind:

	FIXED (`00`)	INCR (`01`)
Address per beat	Same address every beat	Increments by `2^AxSIZE` each beat
Target	One fixed location (FIFO/register)	A contiguous memory range
Max length	16 beats	256 beats (AXI4) / 16 (AXI3)
Typical use	Peripheral FIFO/port streaming	Memory, cache lines, DMA to RAM

Using the wrong one is a real bug: an INCR burst aimed at a FIFO scatters the words across 0x4000, 0x4004, 0x4008, … (hitting whatever those addresses decode to) instead of pushing them all into the one FIFO port; a FIXED burst aimed at memory rewrites the same word AxLEN+1 times, leaving only the last value and corrupting nothing-but-one location.

Figure 4 — FIXED vs INCR addressing. FIXED holds the address at A for every beat (FIFO/register). INCR advances A → A+2^AxSIZE → A+2·2^AxSIZE … (memory range). Choosing the wrong type either scatters FIFO writes across addresses (INCR on a port) or collapses a memory write onto one location (FIXED on memory).

5. Constraints

FIXED has a few hard rules:

Length ≤ 16 beats. FIXED is capped at 16 beats in both AXI3 and AXI4 (it does not get AXI4's 256-beat extension — that's INCR only).
AxSIZE and lanes are constant. Since the address doesn't move, every beat uses the same byte lanes (those the address/size select); a narrow FIXED burst hits the same lanes each beat.
WSTRB still per beat. Each write beat carries its own strobes, so successive pushes can write different byte patterns to the same port if needed.
The 4 KB boundary is trivially satisfied. Because the address never advances, a FIXED burst occupies a single address and cannot cross a 4 KB boundary (Chapter 7.6) — the rule still applies but is automatically met.

6. Common Misconceptions

Myths to unlearn

"FIXED bursts increment slowly / by a small amount." No — FIXED does not increment at all. Every beat uses the same address. Any incrementing burst is INCR.
"FIXED is just an inefficient INCR." They serve different targets. FIXED is correct (and necessary) for a single-port FIFO/register; it's not "INCR done wrong."
"You can do a long FIXED burst like AXI4 INCR." No — FIXED is capped at 16 beats; the 256-beat extension is INCR-only.
"FIXED writes the same data every beat." The address is fixed, not the data — each beat carries its own WDATA/WSTRB, which is the whole point of pushing a stream into a FIFO.
"FIXED to a memory range works, just slowly." It's almost always a bug — every beat overwrites the same memory word, so only the last beat's data survives. Memory ranges need INCR.

7. Debugging Insight

🔍 Debugging insight — FIXED/INCR mismatches scatter or collapse data

FIXED bugs are usually a burst-type mismatch against the target's nature:

FIFO writes landing at scattered addresses / overrunning into neighbours? The burst is INCR when it should be FIXED — the address advanced (0x4000, 0x4004, …) and the words hit ascending locations instead of all entering the one FIFO port. Check AxBURST: a FIFO/port target needs 00 (FIXED).
A memory write where only the last word "took"? The burst is FIXED when it should be INCR — every beat overwrote the same address, so only the final beat's data remains. The target was a range; it needs 01 (INCR).
A FIXED burst longer than 16 beats rejected/misbehaving? FIXED is capped at 16; a longer FIXED burst is illegal (only INCR reaches 256). Split it or rethink the access.
FIFO push order wrong? With FIXED the beat order is the push order — if data lands out of order, suspect data-channel ordering or the FIFO side, not the addressing (the address is constant by definition).

The quick triage: match AxBURST to the target — single port/FIFO/register → FIXED; memory range → INCR. A scatter pattern means INCR-on-a-port; a "only last value survives" means FIXED-on-memory.

8. Verification Insight

✅ Verification insight — assert the address never advances, and the length cap

The FIXED-specific checks are about addressing and limits. Address constancy: assert that across all AxLEN+1 beats the effective address is the same — a reference model for a FIXED burst must apply every beat to the one AxADDR (not a progression), so any beat that lands elsewhere is caught. Length legality: enforce the ≤16-beat cap and flag a FIXED burst that exceeds it. Lane constancy: since the address is fixed, the active byte lanes are the same each beat; check WSTRB/size consistency against that fixed address.

Functionally, model the target correctly: for a FIFO port, the scoreboard should treat AxLEN+1 FIXED beats as AxLEN+1 push/pop operations on the queue (order preserved), not as writes to distinct addresses; verify the queue contents and ordering match the beats. Coverage should include FIXED reads and writes, length 1 through 16, narrow FIXED transfers, and the negative case of a FIXED burst mistakenly aimed at a memory range (to confirm your environment/monitors flag the likely-bug pattern). The address-progression and 4 KB checks from later chapters are trivially satisfied for FIXED but should still be exercised to confirm the monitor handles the degenerate case.

9. Interview Questions

10. Summary

The FIXED burst (AxBURST = 2'b00) is the same-address burst: one address transaction, AxLEN+1 beats, every beat to the one address — no increment. That makes it the right (and necessary) type for a single-location target — a peripheral FIFO or a repeatedly-accessed register — where a DMA streams many words into one hardware port. Everything else is normal: AxSIZE bytes per beat (same lanes each beat), per-beat WSTRB, LAST on the final beat. It's capped at 16 beats (no AXI4 256 extension), and the 4 KB rule is automatically satisfied since the address never moves.

The essential discipline is matching the burst type to the target's nature: single port/FIFO/register → FIXED; contiguous memory range → INCR. Get it backwards and data either scatters across addresses (INCR on a port) or collapses onto one location (FIXED on memory) — and in verification, model a FIXED-to-FIFO target as an ordered queue, not a flat memory cell, or you'll miss dropped/reordered beats. Next: INCR — the incrementing workhorse that handles essentially all memory traffic.

11. What Comes Next

You've got the first burst type; next, the one you'll see most:

7.3 — INCR Bursts (coming next) — the incrementing burst, the workhorse for all memory access, and where the 256-beat length and 4 KB rule come into play.
7.4 — WRAP Bursts (coming soon) — the wrapping burst for cache-line fills.

Previous: 7.1 — Burst Length, Size & Beats. Related: 6.2 — AxBURST for the burst-type selector. For the broader protocol catalog, see the AMBA family overview doc.